Abstract: Provided are an array substrate and a manufacturing method thereof. A first wire of a fanout line of the array substrate is divided into a plurality of first sections. A second wire of the fanout line is divided into a plurality of second sections corresponding to the first sections. Each of the first sections is electrically connected to the second section corresponding thereof. Thus, as a certain position of the first wire or the second wire is broken, only a resistance of the first section or the second section where the broken position is located is changed, so that a blocking effect on the entire fanout lines is not large, thereby reducing or avoiding appearance of a light line.

Abstract: The array substrate taught by the present invention have dummy ITO lines on the fanout lines configured as multiple segments separated at intervals so that, when two neighboring dummy ITO lines are short-circuited, the place of short circuit is limited to a segment of the neighboring dummy ITO lines. Coupling capacitance is limited to that between the segments and fanout lines. Compared to prior arts where coupling capacitance occurs between neighboring dummy ITO lines and fanout lines, the present invention has much smaller coupling capacitance, thereby reducing the impact of coupling capacitance to signal transmission on the fanout lines, avoiding the occurrence of light lines on the display panel, and enhancing the display effect of the display panel.

Abstract: Provided are an array substrate and a manufacturing method thereof. A first wire of a fanout line of the array substrate is divided into a plurality of first sections. A second wire of the fanout line is divided into a plurality of second sections corresponding to the first sections. Each of the first sections is electrically connected to the second section corresponding thereof. Thus, as a certain position of the first wire or the second wire is broken, only a resistance of the first section or the second section where the broken position is located is changed, so that a blocking effect on the entire fanout lines is not large, thereby reducing or avoiding appearance of a light line.

Abstract: The array substrate taught by the present invention have dummy ITO lines on the fanout lines configured as multiple segments separated at intervals so that, when two neighboring dummy ITO lines are short-circuited, the place of short circuit is limited to a segment of the neighboring dummy ITO lines. Coupling capacitance is limited to that between the segments and fanout lines. Compared to prior arts where coupling capacitance occurs between neighboring dummy ITO lines and fanout lines, the present invention has much smaller coupling capacitance, thereby reducing the impact of coupling capacitance to signal transmission on the fanout lines, avoiding the occurrence of light lines on the display panel, and enhancing the display effect of the display panel.