Abstract: A digitally switched impedance has improved linearity by minimizing the amount of impedance error introduced by switches used to switch the impedance elements comprising the digitally switched impedance. Improved settling time of the digitally switched impedance is achieved by reducing the amount of switch capacitance connected to the output of the digitally switched impedance. The digitally switched impedance may be fabricated on an integrated circuit die and the switches may be fabricated with complementary metal oxide semiconductor (CMOS) transistors. The number of impedances needed for a desired number of impedance step changes is reduced by using two major impedance ranks and one minor impedance rank, or two minor impedance ranks and one major impedance rank connected in series.

Abstract: A digitally switched impedance has improved linearity by minimizing the amount of impedance error introduced by switches used to switch the impedance elements comprising the digitally switched impedance. Improved settling time of the digitally switched impedance is achieved by reducing the amount of switch capacitance connected to the output of the digitally switched impedance. The digitally switched impedance may be fabricated on an integrated circuit die and the switches may be fabricated with complementary metal oxide semiconductor (CMOS) transistors. The number of impedances needed for a desired number of impedance step changes is reduced by using two major impedance ranks and one minor impedance rank, or two minor impedance ranks and one major impedance rank connected in series.

Abstract: A digitally switched potentiometer has improved linearity by minimizing the amount of resistive error introduced by switches used to switch the resistive elements comprising the potentiometer. Improved settling time of the potentiometer is achieved by reducing the amount of switch capacitance connected to the output of the potentiometer. The digitally switched potentiometer may be fabricated on an integrated circuit die and the switches may be fabricated with complementary metal oxide semiconductor (CMOS) transistors. The number of resistors needed for a desired number of resistive step changes is reduced by using two major resistor ranks and one minor resistor rank, or two minor resistor ranks and one major resistor rank connected in series.

Abstract: A data processor (21) includes an external bus interface circuit (33) responsive to two internal bus master devices (30, 34) to perform either a fixed or a variable burst access. The data processor (21) activates an external control signal to indicate whether a burst access is a fixed or a variable burst access. The data processor (21) indicates the port size of the accessed memory region by providing a port size signal to the external bus interface circuit (33). The external bus interface circuit (33) is responsive to the port size signal to break up the burst cycle into two or more burst cycles on the external bus (22, 23), if the accessed location corresponds to a memory (24) with a different port size than the internal bus (31).

Abstract: An integrated circuit chip includes a secure memory element that stores secret data, an opaque layer of material encapsulating the chip, and means for eliminating the secret data from the secure memory element in the event that the encapsulation material is removed from the chip. The eliminating means comprise a protective circuit encapsulated by the encapsulation material and coupled to the secure memory element.