Abstract: An interconnect switch is used to couple input ports and output ports. The interconnect switch includes a central buffer having a number of storage entries to store data units from input ports. When an output port is available, data unit(s) are transferred from the central buffer to an output port. A main pointer queue contains addresses that point to storage entries in the central buffer.

Abstract: A method and apparatus of performing transactions over a bus includes sending, from a first device, an indication to start a bus transaction. Assertion of a predetermined indication from a second device is waited for. An indication that the first device is ready to transfer data over the bus is asserted after assertion of the predetermined indication. In one arrangement, the bus is a Peripheral Component Interconnect (PCI) bus.

Abstract: A device is described by this disclosure for performing memory stores in a memory of a computer system. The computer system includes a processor having a pipeline for processing commands in multiple stages; wherein the commands include a plurality of instructions, including store instructions, and virtual addresses. When the processor processes a store command, the pipeline is blocked until the associated virtual address is translated by a translation device to a real address. In the present device, if a selected store operation is processed, a check is made to see if the associated virtual address has previously been translated, and if it has, the pipeline is unblocked, thus enhancing the processing of store operations.