Patents by Inventor Chinh Nguyen

Chinh Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240070400
    Abstract: Method of analysis text message syntactically and by content, which entails: step 1; Split syntaxes (made available to subscribers by the network operator) into tokens to store in a Syntax Trie; step 2. Pre-process an incoming text from a subscriber; step 3. Split the text (pre-processed in Step 2) into tokens; step 4. Look up paths that include the tokens (obtained in Step 3) in the Syntax Trie (initialized in Step 1); step 5: Return the look-up result, which is the path in the Syntax Trie that best reflects the user intent.
    Type: Application
    Filed: August 30, 2023
    Publication date: February 29, 2024
    Applicant: VIETTEL GROUP
    Inventors: Van Chung Trinh, Duc Hai Nguyen, Dinh Hung Nguyen, Hai Son Bui, Duc Anh Nguyen, Thi Huyen Trang Nguyen, Thi Thuy Linh Le, Van Chinh Pham, Van Manh Phan
  • Publication number: 20220367360
    Abstract: A semiconductor device including four transistors. Gates of first and third transistors extend longitudinally as part of a first linear strip. Gates of second and fourth transistors extend longitudinally as part of a second linear strip parallel to and spaced apart from first linear strip. Aligned first and second gate cut isolations separate gates of first and second transistor from gates of third transistor and fourth transistor respectively. First and second CB layers connect to the gate of first transistor and second transistor respectively. CA layer extends longitudinally between first end and second end of CA layer connects to CB layers. CB layers are electrically connected to gates of first transistor adjacent first end of CA layer and second transistor adjacent second end of CA layer respectively. CA layer extends substantially parallel to first and second linear strips and is substantially perpendicular to first and second CB layers.
    Type: Application
    Filed: August 2, 2022
    Publication date: November 17, 2022
    Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 11444031
    Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: September 13, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Publication number: 20210013150
    Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 14, 2021
    Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 10876514
    Abstract: The present invention related to the ocean wave energy exploiting and storing device for electricity generation. The device consists of one hollow pillar (1), the pillar has a base to install the platform (3) and a slot for the hydraulic cylinder (2). The weight-loaded type accumulator (4) is installed within the pillar; two work platform (3) and (13) installed separately which work independently on each other. The first platform (3) covers the head of the pillar above the seal level and can move up and down. The level arm (6) is equipped with the hydraulic cylinder (9 via a swivel join (10). There is a buoy (12) installed on the other end of the level arm. The second platform (13) is placed on the head of the pressing axle (5) above the first one (3).
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: December 29, 2020
    Inventor: Dinh Chinh Nguyen
  • Patent number: 10833018
    Abstract: A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 10731305
    Abstract: A fast installing self-propelled pontoon bridge consisting of the entrance vehicle (A-1), a vehicle-float which is connected with the entrance vehicle and an exit vehicle, an exit vehicle, and an anchoring vehicle to keep the bridge in one place, being equipped with an anchor to keep the pontoon bridge to resist the water flow.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: August 4, 2020
    Inventor: Dinh Chinh Nguyen
  • Publication number: 20190326219
    Abstract: A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Publication number: 20190127931
    Abstract: The invention is about fast installing self-propelled pontoon bridge. The pontoon bridge consists of the entrance vehicle (A-1), vehicle-floats (A-2) connecting the entrance vehicle and the exit vehicle of the bridge (A-3). The anchoring vehicle (A-4) is to moor the bridge to the river bed when installing/uninstalling the bridge. The bodies of the portions are main floats; the vehicles are designed in a way that they can both move on the ground and in the water. For parts associated with moving on the ground, the conventional axles are replaced by the wheels directly driven by hydraulic motors (1). The vehicles' structures are modified to fit new operation methods. The vehicles act as joints. The vehicles are designed for straight line connection; and, the “soft” connecting is carried out before entering the water. Each vehicle can cross the river by itself. Once the exit vehicle of the bridge is approaching the opposite river bank, all the vehicles are connected.
    Type: Application
    Filed: October 15, 2018
    Publication date: May 2, 2019
    Inventor: Dinh Chinh Nguyen
  • Publication number: 20190113018
    Abstract: The present invention related to the ocean wave energy exploiting and storing device for electricity generation. The device consists of one hollow pillar (1), the pillar has a base to install the platform (3) and a slot for the hydraulic cylinder (2). The weight-loaded type accumulator (4) is installed within the pillar; two work platform (3) and (13) installed separately which work independently on each other. The first platform (3) covers the head of the pillar above the sea level and can move up and down. The level arm (6) is equipped with the hydraulic cylinder (9 via a swivel joint (10). There is a buoy (12) installed on the other end of the level arm. The second platform (13) is placed on the head of the pressing axle (5) above the first one (3).
    Type: Application
    Filed: October 15, 2018
    Publication date: April 18, 2019
    Inventor: Dinh Chinh Nguyen
  • Patent number: 10046487
    Abstract: Embodiments of the invention describe methods and apparatus for mixing chemical components in the manufacture of polyurethane foam. The chemical components include a polyol and different blowing agents. The blowing agents are injected directly into a mixing chamber (100) at different height levels according to their boiling points. The mixing chamber allows continuous discharge of the mixture into a static mixer (400) for further mixing before being stored into a storage tank (600). The blowing agents are chemical compounds selected from the group consisting of hydrocarbon-containing compounds, hydrofluorocarbon-containing compounds or hydrofluoroolefin-containing compounds.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: August 14, 2018
    Assignee: RIM Polymers Industries PTE., Ltd.
    Inventors: Van Chinh Nguyen, Choon Min Hoong, Thiam Chye Lee
  • Publication number: 20160268204
    Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.
    Type: Application
    Filed: May 25, 2016
    Publication date: September 15, 2016
    Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 9355910
    Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: May 31, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Publication number: 20160031165
    Abstract: A fiber-laying device is disclosed for laying continuous fiber material which is conveyed from a fiber storage unit to a fiber-laying head which is movable in space. The fiber materials here are guided along the kinematic chain of the robot, wherein an equalization system for equalizing length variations during movement of the robot is provided in the fiber-material storage unit.
    Type: Application
    Filed: July 28, 2015
    Publication date: February 4, 2016
    Inventor: Duy Chinh NGUYEN
  • Publication number: 20150336308
    Abstract: Embodiments of the invention describe methods and apparatus for mixing chemical components in the manufacture of polyurethane foam. The chemical components include a polyol and different blowing agents. The blowing agents are injected directly into a mixing chamber (100) at different height levels according to their boiling points. The mixing chamber allows continuous discharge of the mixture into a static mixer (400) for further mixing before being stored into a storage tank (600). The blowing agents are chemical compounds selected from the group consisting of hydrocarbon-containing compounds, hydrofluorocarbon-containing compounds or hydrofluoroolefin-containing compounds.
    Type: Application
    Filed: June 8, 2011
    Publication date: November 26, 2015
    Inventors: Van Chinh NGUYEN, Choon Min HOONG, Thiam Chye LEE
  • Patent number: 8987128
    Abstract: An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Marc Tarabbia, Chinh Nguyen, David Doman, Juhan Kim, Xiang Qi, Suresh Venkatesan
  • Publication number: 20140027918
    Abstract: An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.
    Type: Application
    Filed: July 30, 2012
    Publication date: January 30, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Marc Tarabbia, Chinh Nguyen, David Doman, Juhan Kim, Xiang Qi, Suresh Venkatesan
  • Publication number: 20140001563
    Abstract: One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Mahbub Rashed, David Doman, Marc Tarabbia, Irene Lin, Jeff Kim, Chinh Nguyen, Steve Soss, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 8618607
    Abstract: One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: December 31, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, David Doman, Marc Tarabbia, Irene Lin, Jeff Kim, Chinh Nguyen, Steve Soss, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 8598633
    Abstract: A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: December 3, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Marc Tarabbia, James B. Gullette, Mahbub Rashed, David S. Doman, Irene Y. Lin, Ingolf Lorenz, Larry Ho, Chinh Nguyen, Jeff Kim, Jongwook Kye, Yuansheng Ma, Yunfei Deng, Rod Augur, Seung-Hyun Rhee, Jason E. Stephens, Scott Johnson, Subramani Kengeri, Suresh Venkatesan