Abstract: An apparatus is provided that includes a memory die including a pipeline circuit coupled to a memory structure. The memory die is configured to execute a first command by receiving in the pipeline circuit data to be written to the memory structure, processing the received data in the pipeline circuit and providing the processed data to the memory structure, predicting that the pipeline circuit has completed processing the received data, and ending execution of the first command based on the prediction.

Abstract: An apparatus is provided that includes a memory die including a pipeline circuit coupled to a memory structure. The memory die is configured to execute a first command by receiving in the pipeline circuit data to be written to the memory structure, processing the received data in the pipeline circuit and providing the processed data to the memory structure, predicting that the pipeline circuit has completed processing the received data, and ending execution of the first command based on the prediction.

Abstract: An output circuit at the output of an LDO regulator has two FETs (Field-Effect Transistors), a current source and a capacitor. The first FET is connected to the LDO output and a second voltage supply. The second FET is connected in series with the current source between the LDO output and the second voltage supply. The second FET is connected to the first FET in such a matter that a bias voltage is supplied to the first FET so that in static conditions the first FET draws predetermined amounts of current from the LDO output and to divert the predetermined amounts of current to the LDO output or to draw additional amounts of current from the LDO output to compensate for transient currents on the LDO output and to reduce variations in the output voltage of the LDO regulator.

Abstract: A differential current sensing circuit architecture is used with an integrated circuit NVM memory block in which a selected memory cell and a related complementary memory cell are accessed at the same time for reading. The circuit architecture is used not only for normal operations for reading the logic states of a selected memory cell and its complementary memory cell after programming, but also for reading the logic states of a selected memory cell and its complementary memory cell before programming for the detecting of faults in memory cells.

Abstract: An output circuit at the output of an LDO regulator has two FETs (Field-Effect Transistors), a current source and a capacitor. The first FET is connected to the LDO output and a second voltage supply. The second FET is connected in series with the current source between the LDO output and the second voltage supply. The second FET is connected to the first FET in such a matter that a bias voltage is supplied to the first FET so that in static conditions the first FET draws predetermined amounts of current from the LDO output and to divert the predetermined amounts of current to the LDO output or to draw additional amounts of current from the LDO output to compensate for transient currents on the LDO output and to reduce variations in the output voltage of the LDO regulator.

Abstract: A differential current sensing circuit architecture is used with an integrated circuit NVM memory block in which a selected memory cell and a related complementary memory cell are accessed at the same time for reading. The circuit architecture is used not only for normal operations for reading the logic states of a selected memory cell and its complementary memory cell after programming, but also for reading the logic states of a selected memory cell and its complementary memory cell before programming for the detecting of faults in memory cells.

Abstract: A method and system for enabling auto shut-off of programming of a non-volatile memory cell is disclosed. The system includes a memory array having a plurality of memory cells, each cell storing one bit of data. During the programming process, programming signals are applied to the target memory cells. A predefined period of time after the programming signals are applied, the auto shut-off system begins sensing an output signal from the memory cell. After the system detects an output signal from the memory cell, the system waits for a second predefined period of time before turning off the programming voltages. The system may be configured to sense an output voltage from the memory cell. The system then compares the output voltage to a reference voltage in order to detect when the cell is programmed. Alternatively, the system may sense an output current from the memory cell. The system then compares the output current to a reference current to detect when the cell is programmed.

Abstract: A method and system for enabling auto shut-off of programming of a non-volatile memory cell is disclosed. The system includes a memory array having a plurality of memory cells, each cell storing one bit of data. During the programming process, programming signals are applied to the target memory cells. A predefined period of time after the programming signals are applied, the auto shut-off system begins sensing an output signal from the memory cell. After the system detects an output signal from the memory cell, the system waits for a second predefined period of time before turning off the programming voltages. The system may be configured to sense an output voltage from the memory cell. The system then compares the output voltage to a reference voltage in order to detect when the cell is programmed. Alternatively, the system may sense an output current from the memory cell. The system then compares the output current to a reference current to detect when the cell is programmed.

Abstract: In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program word line is connected to a memory cell and the memory cell includes a plurality of transistors. In another example embodiment, an unselected memory cell is biased to a negative bias voltage during read operations.

Abstract: In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program word line is connected to a memory cell and the memory cell includes a plurality of transistors. In another example embodiment, an unselected memory cell is biased to a negative bias voltage during read operations.

Abstract: The embodiment of this invention is a retractable spike pin snow tire. The retractable spike pin units are radially embedded in the road contact surface of specially designed vehicle tires. The retractable spike pin unit utilizes SMA (Shape Memory Alloy) actuators to provide mechanical forces for the spike pin. When activated electronically as needed by the driver, or by tire traction sensors, the plurality of spike pins will protrude out from the metal housings. These protruded pins will cling onto the ice covered or snow pressed road surface and provide needed extra grips for tires on slippery road conditions. When not in need the pins will be retracted back into their metal housing electronically by the driver's input, or by sensors.