Patents by Inventor Chinna Prudvi
Chinna Prudvi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8122194Abstract: A processing agent is used in a system that transfers data of a predetermined data line length during external transactions. The agent may include an internal cache having a plurality of cache entries. Each cache entry may store multiple data line lengths of data. The agent further may include a transaction queue system having queue entries that include a primary entry including an address portion and status portion, the status portion provided for a first external transaction of the agent, and a secondary entry including a status portion provided for a second external transaction.Type: GrantFiled: May 19, 2009Date of Patent: February 21, 2012Assignee: Intel CorporationInventors: Chinna Prudvi, Derek T. Bachand
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Publication number: 20100037027Abstract: A processing agent is used in a system that transfers data of a predetermined data line length during external transactions. The agent may include an internal cache having a plurality of cache entries. Each cache entry may store multiple data line lengths of data. The agent further may include a transaction queue system having queue entries that include a primary entry including an address portion and status portion, the status portion provided for a first external transaction of the agent, and a secondary entry including a status portion provided for a second external transaction.Type: ApplicationFiled: May 19, 2009Publication date: February 11, 2010Inventors: Chinna Prudvi, Derek T. Bachand
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Patent number: 7555603Abstract: A processing agent is used in a system that transfers data of a predetermined data line length during external transactions. The agent may include an internal cache having a plurality of cache entries. Each cache entry may store multiple data line lengths of data. The agent further may include a transaction queue system having queue entries that include a primary entry including an address portion and status portion, the status portion provided for a first external transaction of the agent, and a secondary entry including a status portion provided for a second external transaction.Type: GrantFiled: December 16, 1998Date of Patent: June 30, 2009Assignee: Intel CorporationInventors: Chinna Prudvi, Derek T. Bachand
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Patent number: 6735675Abstract: Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.Type: GrantFiled: January 17, 2003Date of Patent: May 11, 2004Assignee: Intel CorporationInventors: Paul D. Breuder, Derek T. Bachand, David Lawrence Hill, Chinna Prudvi
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Publication number: 20030110359Abstract: Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.Type: ApplicationFiled: January 17, 2003Publication date: June 12, 2003Inventors: Paul D. Breuder, Derek T. Bachand, David Lawrence Hill, Chinna Prudvi
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Patent number: 6578114Abstract: Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.Type: GrantFiled: June 26, 2002Date of Patent: June 10, 2003Assignee: Intel CorporationInventors: Paul D. Breuder, Derek T. Bachand, David Lawrence Hill, Chinna Prudvi
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Publication number: 20020156982Abstract: Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.Type: ApplicationFiled: June 26, 2002Publication date: October 24, 2002Inventors: Paul D. Breuder, Derek T. Bachand, David Lawrence Hill, Chinna Prudvi
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Patent number: 6434677Abstract: Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.Type: GrantFiled: June 1, 1999Date of Patent: August 13, 2002Assignee: Intel CorporationInventors: Paul D. Breuder, Derek T. Bachand, David Lawrence Hill, Chinna Prudvi
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Patent number: 6412091Abstract: An error correction system in an agent provides an error correction in a circuit path extending from an internal cache to an output of the agent. When data errors are detected for data to be processed internally within the agent, the error correction system passes the corrupted data through the error correction circuit, and out of the agent and back into the agent. The error correction changes internal data requests into an external transaction when data errors are detected.Type: GrantFiled: May 4, 2001Date of Patent: June 25, 2002Assignee: Intel CorporationInventors: David L. Hill, Chinna Prudvi, Derek T. Bachand, Paul Breuder
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Patent number: 6401172Abstract: A method of processing a data request in a processing agent. The method comprises posting the data request internally within the agent and, if the data request implicates data associated with a pending external transaction, canceling and recycling the data request.Type: GrantFiled: December 18, 1998Date of Patent: June 4, 2002Assignee: Intel Corp.Inventors: Chinna Prudvi, Derek T. Bachand, David L. Hill
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Patent number: 6378048Abstract: A cache coherency method, a data eviction method, and a multi-level cache system are disclosed. A copy of data may take one of five states including a shared state, a lazy state, an invalid state, a modified state, and an exclusive state. Based upon the names of these states, the disclosed methods and systems may be labeled “SLIME.” The method of cache coherency may include storing a copy of data in a cache and storing state information identifying the copy as being stored in one of the five above-mentioned states. In response to a snoop request related to the data, marking a status field indicative of the state of the data to represent that the data is shared without regard to the data's dirty status.Type: GrantFiled: November 12, 1998Date of Patent: April 23, 2002Assignee: Intel CorporationInventors: Chinna Prudvi, Paul Breuder, Quinn W. Merrill, Derek Bachand, Harish kumar Kumar, Brent E. Lince
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Publication number: 20010020286Abstract: An error correction system in an agent provides an error correction in a circuit path extending from an internal cache to an output of the agent. When data errors are detected for data to be processed internally within the agent, the error correction system passes the corrupted data through the error correction circuit, and out of the agent and back into the agent. The error correction changes internal data requests into an external transaction when data errors are detected.Type: ApplicationFiled: May 4, 2001Publication date: September 6, 2001Inventors: David L. Hill, Chinna Prudvi, Derek T. Bachand, Paul Breuder
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Patent number: 6269465Abstract: An error correction system in an agent provides an error correction in a circuit path extending from an internal cache to an output of the agent. When data errors are detected for data to be processed internally within the agent, the error correction system passes the corrupted data through the error correction circuit, and out of the agent and back into the agent. The error correction changes internal data requests into an external transaction when data errors are detected.Type: GrantFiled: November 23, 1998Date of Patent: July 31, 2001Assignee: Intel CorporationInventors: David L. Hill, Chinna Prudvi, Derek T. Bachand, Paul Breuder
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Patent number: 6216208Abstract: A prefetching control system provided for a processor. The prefetching queue may include an arbiter, a cache queue and a prefetch queue. The arbiter issues requests including read requests. Responsive to a read request, the cache queue issues a control signal. The prefetch queue receives the control signal and an address associated with the read request. When the received address is a member of a pattern of read requests from sequential memory locations, the prefetch queue issues a prefetch request to the arbiter.Type: GrantFiled: December 29, 1997Date of Patent: April 10, 2001Assignee: Intel CorporationInventors: Robert Greiner, David L. Hill, Chinna Prudvi, Derek T. Bachand, Matthew A. Fisch
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Patent number: 6209068Abstract: A data control method in a microprocessor is disclosed. According to the method, a request is generated on an external bus for data to be read to the processor. The requested data is read from the external bus to an intermediate memory in the processor and, thereafter, read from the intermediate memory to a destination. When the intermediate memory is full, the read of data from the external bus is stalled until the intermediate memory is no longer full. Typically, stalling is accomplished by generating a stall signal on the external bus, which may be generated during a cache coherency phase of the transaction to which the requested data relates.Type: GrantFiled: December 29, 1997Date of Patent: March 27, 2001Assignee: Intel CorporationInventors: David L. Hill, Chinna Prudvi, Derek T. Bachand, Matthew A. Fisch
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Patent number: 6078981Abstract: A livelock preventative measure is provided for agents in a multi-processor computing system. Livelock may occur when multiple agents each trade ownership of data in an attempt to modify it. When livelock occurs, a first agent posts a bus transaction for a data and, if a second agent posts a bus transaction for the same data, the first agent may stall the bus transaction of the second agent until the first agent has completed its operation on the data.Type: GrantFiled: December 29, 1997Date of Patent: June 20, 2000Assignee: Intel CorporationInventors: David L. Hill, Chinna Prudvi, Derek T. Bachand, Paul Breuder, Matthew A. Fisch