Abstract: In accordance with embodiments, there are provided mechanisms and methods for recovering from an incomplete transaction. These mechanisms and methods can enable embodiments to detect incomplete transactions when recovering from a server crash or other catastrophic event. Some embodiments can automatically re-establish interrupted connections when incomplete transactions have been detected. The ability of embodiments to detect incomplete transaction can allow recovery to initiate substantially immediately upon server restart and adapter redeployment.

Abstract: In accordance with embodiments, there are provided mechanisms and methods for substituting a new version resource adaptor for a production version of the resource adaptor. These mechanisms and methods can enable embodiments to provide upgrade to a new version resource adaptor contemporaneous with completion of work by the production version of the resource adaptor. The ability of embodiments to provide upgrade to a new version resource adaptor contemporaneous with completion of work by the production version of the resource adaptor can enable an installation desiring to install a new component of their connector system while the system remains in production, eliminating the need to halt the system, i.e., stop all traffic, replace the production version of the component with an upgraded version, test and finally place the upgraded version into production.

Abstract: In accordance with embodiments, there are provided mechanisms and methods for suspending work by a resource adapter. These mechanisms and methods for suspending work by a resource adapter can enable embodiments to provide the capability to start and stop work performed by a resource adapter to connector architectures. The ability of embodiments to provide the capability to start and stop work performed by a resource adapter can enable users of Connector Architectures to quiesce an adapter's inbound/outbound or work sections. Such capability can enable an adapter embodiment to complete in-flight transactions but not accept new inbound transactions until a request to resume operation is received. Resource adapters may be quiesced during a versioning or change out process or other maintenance processes for example.

Abstract: Methods and apparatus for dynamic packet mapping. A method is provided for mapping metric data to produce a decodable packet associated with a channel. The method includes obtaining a channel identifier associated with metric data, determining an available buffer from a plurality of buffers based on the channel identifier, writing the metric data to the available buffer, detecting when a decodable packet is formed in a selected buffer of the plurality of buffers, and outputting the decodable packet from the selected buffer. An apparatus includes a plurality of buffers and mapping logic that is configured to obtain a channel identifier associated with metric data, determine an available buffer based on the channel identifier, write the metric data to the available buffer, detect when a decodable packet is formed in a selected buffer, and output the decodable packet from the selected buffer.

Abstract: Methods and apparatus for dynamic packet reordering. In an aspect, a method is provided for processing slot data on-the-fly to produce decodable packets, wherein the slot data includes interleaved modulation symbols. The method includes de-interleaving a stream of the interleaved modulation symbols to produce a stream of modulation symbols, calculating parallel streams of LLR metrics based on the stream of modulation symbols, and mapping the parallel streams of LLR metrics to produce a stream of decodable packets. In another aspect, an apparatus is provided the includes de-interleaving logic to de-interleave a stream of interleaved modulation symbols to produce a stream of modulation symbols, metric processing logic configured to produce parallel streams of LLR metrics based on the stream of modulation symbols, and mapping logic configured to map the parallel streams of LLR metrics to produce a stream of decodable packets.

Abstract: Apparatus and methods for estimating the frequency of a sleep or slow clock using a fast clock, such as a temperature compensated crystal oscillator. The disclosed apparatus include an estimator having a first counter that receives sleep clock synchronized pulses issuing each cycle of the sleep clock period, yet are synchronized to a fast clock. The slow clock synchronized pulses are counted up to a predetermined number; whereupon a full count signal is issued. A second counter receives the full count signal and increments each time the full count signal is received. A third counter counts fast clock cycles until the full count signal occurs. Based on the number of counts of the slow and fast clock cycles, the frequency of the slow clock may be determined using only the domain of the fast clock for performing the measurement thereby tying accuracy of the measurement to the accuracy of the fast clock.

Abstract: Disclosed are apparatus and methods for control of sleep modes in a transceiver or receiver. In particular, a transceiver is disclosed including a processor configured to determine timing information concerning sleep periods for at least a portion of components within the transceiver. The transceiver also includes a sleep control logic coupled to the processor to receive information concerning sleep periods from the processor and configured to effect shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.

Abstract: Conserving power for coded transmissions comprises ceasing to process parity packets once associated data packets are deemed correct or corrected. Once data packets are deemed correct or corrected, the receiving unit can shut off during the transmission of parity packets.

Abstract: A Fast Fourier Transform (FFT) hardware implementation and method provides efficient FFT processing while minimizing the die area needed in an Integrated Circuit (IC). The FFT hardware can implement an N point FFT, where N=rn is a function of a radix (r). The hardware implementation includes a sample memory having N/r rows, each storing r samples. A twiddle factor memory can store k twiddle factors per row, where 0<k<r represents the number of complex twiddle multipliers available. An FFT module reads r rows from memory, performs an r-point complex FFT on the samples, followed by twiddle multiplication, and writes the results into an r×r register bank. The contents of the register bank are written in transposed order back to the sample memory. This operation is repeated N/r2 times for each stage and then repeated for n-stages to produce the N point FFT.

Abstract: In addition to global index chunks that indicate the order of program portions in a multimedia stream carrying multiple multiplexed programs, index blocks are provided in data chunks of the stream that point to times when particular program portions arrive. This information can be used at the physical or transport layer of a wireless battery-powered receiver by, e.g., a simple state machine to energize the analog receiving circuitry only for as long as necessary to receive information pertaining to a desired program, thereby conserving battery power.