Patents by Inventor Chintamani Keshav Bhaktavatson

Chintamani Keshav Bhaktavatson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Glitch reduced compensated circuits and methods for using such
    Patent number: 7550993
    Abstract: Various embodiments of the present invention provide systems and methods for glitch reduced circuits. As one example, a glitch reduced, variable width driver circuit is disclosed. Such circuits include a data output, and at least two transistors that each includes a gate, a first leg and a second leg. The gate of the first transistor is electrically coupled to a first combined control signal, and the gate of the second transistor is electrically coupled to a second combined control signal. The first leg of the first transistor and the first leg of the second transistor are electrically coupled to a power source, and the second leg of the first transistor and the second leg of the second transistor are electrically coupled to an output signal. The circuits further include a control circuit that combines a first control signal with the data output to create the first combined control signal, and combines a second control signal with the data output to create the second combined control signal.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: June 23, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Keerthinarayan P. Heragu, Rajat Chauhan, Chintamani Keshav Bhaktavatson
  • GLITCH REDUCED COMPENSATED CIRCUITS AND METHODS FOR USING SUCH
    Publication number: 20090051390
    Abstract: Various embodiments of the present invention provide systems and methods for glitch reduced circuits. As one example, a glitch reduced, variable width driver circuit is disclosed. Such circuits include a data output, and at least two transistors that each includes a gate, a first leg and a second leg. The gate of the first transistor is electrically coupled to a first combined control signal, and the gate of the second transistor is electrically coupled to a second combined control signal. The first leg of the first transistor and the first leg of the second transistor are electrically coupled to a power source, and the second leg of the first transistor and the second leg of the second transistor are electrically coupled to an output signal. The circuits further include a control circuit that combines a first control signal with the data output to create the first combined control signal, and combines a second control signal with the data output to create the second combined control signal.
    Type: Application
    Filed: September 21, 2007
    Publication date: February 26, 2009
    Inventors: Keerthinarayan P. Heragu, Rajat Chauhan, Chintamani Keshav Bhaktavatson