Patents by Inventor Chintan S. Patel
Chintan S. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240103754Abstract: Systems, apparatuses, and methods for prefetching data by a display controller. From time to time, a performance-state change of a memory are performed. During such changes, a memory clock frequency is changed for a memory subsystem storing frame buffer(s) used to drive pixels to a display device. During the performance-state change, memory accesses may be temporarily blocked. In order to reduce visual artifacts that may occur while the memory accesses are blocked, a memory subsystem includes a control circuit configured to enable a caching mode which caches display data provided to the display controller. Subsequent requests for display data from the display controller are then serviced using the cached data instead of accessing memory.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Inventors: Gia Tung Phan, Ashish Jain, Chintan S. Patel, Benjamin Tsien, Jun Lei, Shang Yang, Oswin Hall
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Patent number: 11899520Abstract: A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.Type: GrantFiled: April 26, 2022Date of Patent: February 13, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Ashish Jain, Benjamin Tsien, Chintan S. Patel, Vydhyanathan Kalyanasundharam, Shang Yang
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Patent number: 11874774Abstract: A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.Type: GrantFiled: September 24, 2020Date of Patent: January 16, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Ravindra N. Bhargava, Ganesh Balakrishnan, Joe Sargunaraj, Chintan S. Patel, Girish Balaiah Aswathaiya, Vydhyanathan Kalyanasundharam
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Publication number: 20230418745Abstract: A technique for operating a cache is disclosed. The technique includes utilizing a first portion of a cache in a directly accessed manner; and utilizing a second portion of the cache as a cache.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Chintan S. Patel, Vydhyanathan Kalyanasundharam, Benjamin Tsien, Alexander J. Branover
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Publication number: 20230418753Abstract: A technique for operating a cache is disclosed. The technique includes based on a workload change, identifying a first allocation permissions policy; operating the cache according to the first allocation permissions policy; based on set sampling, identifying a second allocation permissions policy; and operating the cache according to the second allocation permissions policy.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Chintan S. Patel, Alexander J. Branover, Benjamin Tsien, Edgar Munoz, Vydhyanathan Kalyanasundharam
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Patent number: 11822484Abstract: A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width, and stores the data bus inversion information along with selected inverted data words for the cache line fill in the cache memory.Type: GrantFiled: December 20, 2021Date of Patent: November 21, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Vydhyanathan Kalyanasundharam, John Wuu, Chintan S. Patel
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Publication number: 20230341922Abstract: A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.Type: ApplicationFiled: April 26, 2022Publication date: October 26, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Ashish Jain, Benjamin Tsien, Chintan S. Patel, Vydhyanathan Kalyanasundharam, Shang Yang
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Patent number: 11755477Abstract: A cache includes an upstream port, a downstream port, a cache memory, and a control circuit. The control circuit temporarily stores memory access requests received from the upstream port, and checks for dependencies for a new memory access request with older memory access requests temporarily stored therein. If one of the older memory access requests creates a false dependency with the new memory access request, the control circuit drops an allocation of a cache line to the cache memory for the older memory access request while continuing to process the new memory access request.Type: GrantFiled: December 28, 2021Date of Patent: September 12, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Chintan S. Patel, Girish Balaiah Aswathaiya
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Publication number: 20230195644Abstract: A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory controller, and based on detecting an idle condition in the monitored traffic, to cause the memory controller to command the volatile memory to enter self-refresh mode while the last level cache maintains an operational power state and responds to cache hits over the data fabric.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Chintan S. Patel, Guhan Krishnan, Andrew William Lueck, Sreenath Thangarajan
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Publication number: 20230195642Abstract: A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width, and stores the data bus inversion information along with selected inverted data words for the cache line fill in the cache memory.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Vydhyanathan Kalyanasundharam, John Wuu, Chintan S. Patel
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Publication number: 20230105709Abstract: A cache includes an upstream port, a downstream port, a cache memory, and a control circuit. The control circuit temporarily stores memory access requests received from the upstream port, and checks for dependencies for a new memory access request with older memory access requests temporarily stored therein. If one of the older memory access requests creates a false dependency with the new memory access request, the control circuit drops an allocation of a cache line to the cache memory for the older memory access request while continuing to process the new memory access request.Type: ApplicationFiled: December 28, 2021Publication date: April 6, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Chintan S. Patel, Girish Balaiah Aswathaiya
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Publication number: 20230090126Abstract: Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Alexander J. Branover, Christopher T. Weaver, Indrani Paul, Mihir Shaileshbhai Doctor, John P. Petry, Stephen V. Kosonocky, Thomas J. Gibney, Jose G. Cruz, Pravesh Gupta, Chintan S. Patel
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Patent number: 11580025Abstract: Systems and methods for coordinated memory-side cache prefetching and dynamic interleaving configuration modification involve modifying one or both of the prefetch distance or the prefetch degree used by prefetcher modules of one or more memory-side caches by modifying interleaving configuration data following detection of an interleaving reconfiguration trigger condition indicative, for example, of low prefetch accuracy, low prefetch coverage, high prefetch lateness, or a combination of these. In response an interleaving reconfiguration trigger condition, a processor modifies the interleaving configuration data for the processing system based on the prefetch performance characteristics associated with the interleaving reconfiguration trigger condition. In some embodiments, the interleaving configuration data is modified by changing which physical memory address indices are used to determine the bits that define the channel identification number to which that physical memory address is to be mapped.Type: GrantFiled: September 30, 2021Date of Patent: February 14, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Tarun Nakra, Akhil Arunkumar, Vydhyanathan Kalyanasundharam, Chintan S. Patel, Nithesh Kurella Lakshmi Narayanamurthy
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Patent number: 11422935Abstract: A method of controlling a cache is disclosed. The method comprises receiving a request to allocate a portion of memory to store data. The method also comprises directly mapping a portion of memory to an assigned contiguous portion of the cache memory when the request to allocate a portion of memory to store the data includes a cache residency request that the data continuously resides in cache memory. The method also comprises mapping the portion of memory to the cache memory using associative mapping when the request to allocate a portion of memory to store the data does not include a cache residency request that data continuously resides in the cache memory.Type: GrantFiled: September 25, 2020Date of Patent: August 23, 2022Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Chintan S. Patel, Vydhyanathan Kalyanasundharam, Benjamin Tsien
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Patent number: 11289131Abstract: Systems, apparatuses, and methods for implementing dynamic control of a multi-region fabric are disclosed. A system includes at least one or more processing units, one or more memory devices, and a communication fabric coupled to the processing unit(s) and memory device(s). The system partitions the fabric into multiple regions based on different traffic types and/or periodicities of the clients connected to the regions. For example, the system partitions the fabric into a stutter region for predictable, periodic clients and a non-stutter region for unpredictable, non-periodic clients. The system power-gates the entirety of the fabric in response to detecting a low activity condition. After power-gating the entirety of the fabric, the system periodically wakes up one or more stutter regions while keeping the other non-stutter regions in power-gated mode. Each stutter region monitors stutter client(s) for activity and processes any requests before going back into power-gated mode.Type: GrantFiled: December 7, 2020Date of Patent: March 29, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Alexander J. Branover, Alan Dodson Smith, Chintan S. Patel
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Publication number: 20220091991Abstract: A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.Type: ApplicationFiled: September 24, 2020Publication date: March 24, 2022Inventors: Ravindra N. Bhargava, Ganesh Balakrishnan, Joe Sargunaraj, Chintan S. Patel, Girish Balaiah Aswathaiya, Vydhyanathan Kalyanasundharam
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Publication number: 20210406177Abstract: A method of controlling a cache is disclosed. The method comprises receiving a request to allocate a portion of memory to store data. The method also comprises directly mapping a portion of memory to an assigned contiguous portion of the cache memory when the request to allocate a portion of memory to store the data includes a cache residency request that the data continuously resides in cache memory. The method also comprises mapping the portion of memory to the cache memory using associative mapping when the request to allocate a portion of memory to store the data does not include a cache residency request that data continuously resides in the cache memory.Type: ApplicationFiled: September 25, 2020Publication date: December 30, 2021Applicant: Advanced Micro Devices, Inc.Inventors: Chintan S. Patel, Vydhyanathan Kalyanasundharam, Benjamin Tsien
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Publication number: 20210090613Abstract: Systems, apparatuses, and methods for implementing dynamic control of a multi-region fabric are disclosed. A system includes at least one or more processing units, one or more memory devices, and a communication fabric coupled to the processing unit(s) and memory device(s). The system partitions the fabric into multiple regions based on different traffic types and/or periodicities of the clients connected to the regions. For example, the system partitions the fabric into a stutter region for predictable, periodic clients and a non-stutter region for unpredictable, non-periodic clients. The system power-gates the entirety of the fabric in response to detecting a low activity condition. After power-gating the entirety of the fabric, the system periodically wakes up one or more stutter regions while keeping the other non-stutter regions in power-gated mode. Each stutter region monitors stutter client(s) for activity and processes any requests before going back into power-gated mode.Type: ApplicationFiled: December 7, 2020Publication date: March 25, 2021Inventors: Benjamin Tsien, Alexander J. Branover, Alan Dodson Smith, Chintan S. Patel
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Patent number: 10861504Abstract: Systems, apparatuses, and methods for implementing dynamic control of a multi-region fabric are disclosed. A system includes at least one or more processing units, one or more memory devices, and a communication fabric coupled to the processing unit(s) and memory device(s). The system partitions the fabric into multiple regions based on different traffic types and/or periodicities of the clients connected to the regions. For example, the system partitions the fabric into a stutter region for predictable, periodic clients and a non-stutter region for unpredictable, non-periodic clients. The system power-gates the entirety of the fabric in response to detecting a low activity condition. After power-gating the entirety of the fabric, the system periodically wakes up one or more stutter regions while keeping the other non-stutter regions in power-gated mode. Each stutter region monitors stutter client(s) for activity and processes any requests before going back into power-gated mode.Type: GrantFiled: October 5, 2017Date of Patent: December 8, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Alexander J. Branover, Alan Dodson Smith, Chintan S. Patel
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Publication number: 20200259747Abstract: Systems, apparatuses, and methods for dynamic buffer management in multi-client token flow control routers are disclosed. A system includes at least one or more processing units, a memory, and a communication fabric with a plurality of routers coupled to the processing unit(s) and the memory. A router servicing multiple active clients allocates a first number of tokens to each active client. The first number of tokens is less than a second number of tokens needed to saturate the bandwidth of each client to the router. The router also allocates a third number of tokens to a free pool, with tokens from the free pool being dynamically allocated to different clients. The third number of tokens is equal to the difference between the second number of tokens and the first number of tokens. An advantage of this approach is reducing the amount of buffer space needed at the router.Type: ApplicationFiled: February 19, 2020Publication date: August 13, 2020Inventors: Alan Dodson Smith, Chintan S. Patel, Eric Christopher Morton, Vydhyanathan Kalyanasundharam, Narendra Kamat