Abstract: The various embodiments of the present invention provide a method and system for providing random sequence coverage. The method comprising receiving a plurality of data packet packets carrying transaction data from a transaction database, specifying transactions in a configuration file along with the transaction data, identifying one or more fields in the packets received from the transaction database, generating an automatic random sequence based on the identification of at least one of a field among the one or more fields in the data packets, generating a coverage report for the random sequence generated automatically and determining uncovered sequences based on the coverage report generated.

Abstract: The various embodiments of the present invention provide a method for automatically generating a unique set of test vectors for verifying design intent of integrated circuit chips. The method includes obtaining configuration parameters associated with a plurality of integrated circuit chips, generating an Executable Verification Plan pertaining to the configuration parameters of a plurality of integrated circuit chips in one or more execution PCs (EPs), creating a plurality of data structures corresponding to the configuration parameters, communicating the data structures created to a DCMS server, mapping the data structures of the Execution PCs with one or more data structures present in a database of the DCMS server, customizing the executable verification plan based on changes in the configurations of the integrated circuit chips, generating a unique set of test vectors based on mapping of the data structures and performing automatic design verification of the plurality of integrated circuit chips.

Abstract: The various embodiments of the present invention provide a method and system for providing random sequence coverage. The method comprising receiving a plurality of data packet packets carrying transaction data from a transaction database, specifying transactions in a configuration file along with the transaction data, identifying one or more fields in the packets received from the transaction database, generating an automatic random sequence based on the identification of at least one of a field among the one or more fields in the data packets, generating a coverage report for the random sequence generated automatically and determining uncovered sequences based on the coverage report generated.

Abstract: The various embodiments of the present invention provide a method for automatically generating a unique set of test vectors for verifying design intent of integrated circuit chips. The method includes obtaining configuration parameters associated with a plurality of integrated circuit chips, generating an Executable Verification Plan pertaining to the configuration parameters of a plurality of integrated circuit chips in one or more execution PCs (EPs), creating a plurality of data structures corresponding to the configuration parameters, communicating the data structures created to a DCMS server, mapping the data structures of the Execution PCs with one or more data structures present in a database of the DCMS server, customizing the executable verification plan based on changes in the configurations of the integrated circuit chips, generating a unique set of test vectors based on mapping of the data structures and performing automatic design verification of the plurality of integrated circuit chips.