Abstract: Reference scaling, op amp balancing and chopper stabilization techniques for delta-sigma modulators of analog-to-digital converters are provided. For reference scaling, unit elements in a feedback digital-to-analog (DAC) converter are driven by a reference voltage or disconnected from active circuitry to realize three DAC levels. While disconnected, the unit elements deliver no charge to the device which results in power saving and a reduction in thermal noise. Op amp balancing involves down-sampling the quantizer output followed by up-sampling on the feedback path and filtering to hold a DAC value of the signal for a duration of a sampling period to generate the feedback signal. Chopper stabilization is performed by chopping an operational transconductance amplifier of the integrator at a chopping frequency equal to the sampling frequency.

Abstract: A method for determining a phase position of a rotation rate or quadrature signal of a rotation rate sensor. The rotation rate sensor include an oscillatory system which is excited to a drive oscillation and by rotations of the sensor to a detection oscillation. In a first step, a detection signal is ascertained over a time interval, the detection signal reflecting an amplitude of the detection oscillation as a function of time, in a second step, the detection signal is separated into a first and a second signal component, the first and the second signal component being statistically independent of one another, and in a third step, the phase position of the rotation rate signal or the quadrature signal is ascertained as a function of the first signal component and/or the second signal component. A method for adapting a demodulation phase and a rotation rate sensor are also provided.

Abstract: In a digital gyroscope, the rate signal (including the quadrature) and the displacement signal of the drive part are sampled with an ADC. This displacement signal has the same frequency and phase as the quadrature signal that gets sampled in the rate channels. The displacement signal is sampled with the same clock as the rate signal resulting in the displacement signal having the same close-in phase noise folded into the signal band as the sampled quadrature in the rate signal. The sampled drive signal is subtracted from the sampled rate signal to eliminate the clock jitter induced noise in the rate signal. This relaxes the close-in phase noise requirement of the PLL and allows for a low power PLL implementation.

Abstract: Reference scaling, op amp balancing and chopper stabilization techniques for delta-sigma modulators of analog-to-digital converters are provided. For reference scaling, unit elements in a feedback digital-to-analog (DAC) converter are driven by a reference voltage or disconnected from active circuitry to realize three DAC levels. While disconnected, the unit elements deliver no charge to the device which results in power saving and a reduction in thermal noise. Op amp balancing involves down-sampling the quantizer output followed by up-sampling on the feedback path and filtering to hold a DAC value of the signal for a duration of a sampling period to generate the feedback signal. Chopper stabilization is performed by chopping an operational transconductance amplifier of the integrator at a chopping frequency equal to the sampling frequency.

Abstract: A stacked switched resistance device has been developed. The stacked switched resistance device includes a plurality of segments connected in series. Each segment includes a resistor including an inherent parasitic capacitance, and a switch connected in series with the resistor, the switch being configured to connect and disconnect the resistor from the plurality of segments in response to a predetermined clock signal. An effective resistance of the stacked switched resistance device exceeds another effective resistance of at least one resistor with an equivalent inherent resistance that is connected in series to a single switch configured to connect and disconnect the at least one resistor in response to the predetermined clock signal.

Abstract: A current sensing system and delta sigma modulator architecture are discloses for sensing and digitizing a current input signal from a high impedance signal source with improve power efficiency. The delta sigma modulator integrates a signal condition stage within the delta sigma modulator feedback loop by utilizing a capacitive summation stage. For given gain, resolution, and bandwidth requirements, the delta sigma modulator architecture achieves reduced power consumption by advantageously reducing the number of nodes in the system that require a high dynamic range. Additionally, the delta sigma modulator has very high input impedance such that the input of the delta-sigma modulator can be connected directly to a high impedance signal source, without the need for a front-end pre-amplifier stage, or the like.

Abstract: A system for processing signals from a gyroscope includes at least one drive channel and at least one sense channel. The drive channel includes an analog-to-digital converter (ADC), an in-phase demodulator, at least one filter and a phase-locked loop. The sense channel includes an ADC, an in-phase demodulator, a quadrature-phase demodulator, and filters for the in-phase and quadrature-phase demodulators. The system includes a digital subtraction circuit subtract an in-phase component of the drive signal from the drive channel from an in-phase component of the rate signal from the sense channel to generate a sense axis output signal.

Abstract: A variable high voltage charge-pump system includes a plurality of unregulated switching stages and a plurality of regulated switching stages arranged in a cascaded configuration. The unregulated switching stages receive unregulated voltage input signals, and the regulated switching stages receive regulated voltage input signals. An amplifier generates the regulated voltage input signals to bring the output voltage to a desired value.

Abstract: A stacked switched resistance device has been developed. The stacked switched resistance device includes a plurality of segments connected in series. Each segment includes a resistor including an inherent parasitic capacitance, and a switch connected in series with the resistor, the switch being configured to connect and disconnect the resistor from the plurality of segments in response to a predetermined clock signal. An effective resistance of the stacked switched resistance device exceeds another effective resistance of at least one resistor with an equivalent inherent resistance that is connected in series to a single switch configured to connect and disconnect the at least one resistor in response to the predetermined clock signal.

Abstract: A microphone biasing circuit comprises a microphone connected between a first node and a first DC bias voltage, the microphone configured to provide a sensed voltage at the first node in response to sound; a first diode and a second diode, the first diode and the second diode connected antiparallel with one another between the first node and a second node, the second node having a second DC bias voltage; an amplifier having an input connected to the first node and an output connected to a third node, the amplifier configured to provide an output voltage to the third node based on the sensed voltage at the first node; and a feedback path connected from the third node to the second node. The feedback path comprises at least one element configured to couple alternating components of the output voltage at the third node to the second node.

Abstract: A microphone biasing circuit comprises a first amplifier having an output connected to a first node and an input connected to a second node; and a first feedback path connected from the first node to the second node. The first feedback path comprises a microphone having a first terminal connected to the first node and a second terminal connected to a third node, the microphone being configured to provide a sensed voltage at the first node in response to sound, the third node having a first DC bias voltage; and a first capacitor connected between the third node and the second node.

Abstract: A microphone biasing circuit comprises a microphone connected between a first node and a first DC bias voltage, the microphone configured to provide a sensed voltage at the first node in response to sound; a first diode and a second diode, the first diode and the second diode connected antiparallel with one another between the first node and a second node, the second node having a second DC bias voltage; an amplifier having an input connected to the first node and an output connected to a third node, the amplifier configured to provide an output voltage to the third node based on the sensed voltage at the first node; and a feedback path connected from the third node to the second node. The feedback path comprises at least one element configured to couple alternating components of the output voltage at the third node to the second node.

Abstract: A microphone biasing circuit comprises a first amplifier having an output connected to a first node and an input connected to a second node; and a first feedback path connected from the first node to the second node. The first feedback path comprises a microphone having a first terminal connected to the first node and a second terminal connected to a third node, the microphone being configured to provide a sensed voltage at the first node in response to sound, the third node having a first DC bias voltage; and a first capacitor connected between the third node and the second node.

Abstract: A method and system for providing increased accuracy in a CMOS sensor system in one embodiment includes a plurality of sensor elements having a first terminal and a second terminal on a complementary metal oxide semiconductor substrate, a first plurality of switches configured to selectively connect the first terminal to a power source and to selectively connect the first terminal to a readout circuit, and a second plurality of switches configured to selectively connect the second terminal to the power source and to selectively connect the second terminal to the readout circuit.

Abstract: A vertical Hall Effect sensor is provided having a high degree of symmetry between its bias modes, can be adapted to exhibit a small pre-spinning systematic offset, and complies with the minimal spacing requirements allowed by the manufacturing technology (e.g., CMOS) between the inner contacts. These characteristics enable the vertical Hall Effect sensor to have optimal performance with regard to offset and sensitivity.

Abstract: A vertical Hall Effect sensor is provided having a high degree of symmetry between its bias modes, can be adapted to exhibit a small pre-spinning systematic offset, and complies with the minimal spacing requirements allowed by the manufacturing technology (e.g., CMOS) between the inner contacts. These characteristics enable the vertical Hall Effect sensor to have optimal performance with regard to offset and sensitivity.

Abstract: A magnetic field measuring system is disclosed. The magnetic field measuring system includes a substrate, a conductive well formed in the substrate, the well having a first side with a first length, a first contact electrically coupled to the conductive well at a first location of the first side, a second contact electrically coupled to the conductive well at a second location of the first side, wherein the distance between the first location and the second location is less than the first length, a stimulus circuit coupled to the first contact and the second contact, and a sensor for identifying a property indicative of the length of a current path from the first location to the second location through the conductive well.

Abstract: A voltage sensing circuit includes a voltage to current converter, an integrator, a sample and hold amplifier, and a modulator. The voltage to current converter produces a modulated current corresponding to an input voltage. The integrator demodulates the modulated current and produces a voltage sum of the demodulated current. The sample and hold amplifier samples the voltage sum and provides an output voltage corresponding to the voltage sum. The modulator modulates the output voltage and provides the modulated voltage to the voltage to current converter as a feedback voltage.

Abstract: A voltage sensing circuit includes a voltage to current converter, an integrator, a sample and hold amplifier, and a modulator. The voltage to current converter produces a modulated current corresponding to an input voltage. The integrator demodulates the modulated current and produces a voltage sum of the demodulated current. The sample and hold amplifier samples the voltage sum and provides an output voltage corresponding to the voltage sum. The modulator modulates the output voltage and provides the modulated voltage to the voltage to current converter as a feedback voltage.

Abstract: A magnetic field measuring system is disclosed. The magnetic field measuring system includes a substrate, a conductive well formed in the substrate, the well having a first side with a first length, a first contact electrically coupled to the conductive well at a first location of the first side, a second contact electrically coupled to the conductive well at a second location of the first side, wherein the distance between the first location and the second location is less than the first length, a stimulus circuit coupled to the first contact and the second contact, and a sensor for identifying a property indicative of the length of a current path from the first location to the second location through the conductive well.