Abstract: A method for flattening a three-dimensional shoe upper template is provided. The method includes providing a three-dimensional last model, obtaining a three-dimensional grid model, obtaining a three-dimensional thickened grid model, obtaining a two-dimensional initial-value grid model, and obtaining a two-dimensional grid model with the smallest energy value. A system and a non-transitory computer-readable medium for performing the method are also provided. The method makes it possible to precisely flatten a three-dimensional last model with a non-developable surface and thereby convert the three-dimensional last model into a two-dimensional grid model.

Abstract: This invention provides a shoe upper design model generating method, system and non-transitory computer readable storage media, including steps of providing a 2D mapping boundary, providing a 3D upper, performing a flattening algorithm on the 3D upper with respect to the 2D mapping boundary, constructing a 2D upper boundary, creating an upper design drawing on the 2D upper boundary, intersecting the 2D upper boundary and the 2D mapping boundary to form a 2D upper design area and mapping grids in the 2D upper design area onto grids in the 3D upper, thereby obtaining an upper design model containing the mapping relation between the 2D upper design area and the 3D upper. Accordingly, the upper pattern making time and cost can be saved, and the distortion and deformation in the process of 2D-3D conversion can be reduced, thus the completed 2D upper design drawing can be used in production process directly.

Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

Abstract: A method for flattening a three-dimensional shoe upper template is provided. The method includes providing a three-dimensional last model, obtaining a three-dimensional grid model, obtaining a three-dimensional thickened grid model, obtaining a two-dimensional initial-value grid model, and obtaining a two-dimensional grid model with the smallest energy value. A system and a non-transitory computer-readable medium for performing the method are also provided. The method makes it possible to precisely flatten a three-dimensional last model with a non-developable surface and thereby convert the three-dimensional last model into a two-dimensional grid model.

Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

Abstract: A cellulase having improved enzymatic activity is disclosed. The cellulase has a modified amino acid sequence of SEQ ID NO: 2 or a modified amino acid sequence with at least 80% sequence identity of SEQ ID NO: 2, wherein the modification is a substitution of methionine at position 120 or a corresponding position with asparagine.

Abstract: An electrical connector for soldering to a printed circuit board includes an insulative housing, a number of conductive terminals affixed to the insulative housing, and a metal shell surrounding the base portion. The insulative housing includes a base portion. Each conductive terminal includes a soldering portion extending laterally and outwardly from a lateral edge of the base portion. The metal shell includes a pair of longitudinal wall. The electrical connector includes an isolation block isolating the soldering portion from the longitudinal wall of the metal shell in a vertical direction.

Abstract: A multi-layer circuit member includes: a first layer formed of a conductive material, the first layer including plural signal pads and a first reference plane spaced apart from the signal pads, the first reference plane including an outer region surrounding the signal pads and an inner region separating the plurality of signal pads; a second layer formed of a conductive material, the second layer including plural signal conductors and a second reference plane spaced apart from the signal conductors, the second reference plane including an outer region surrounding the signal conductors and an inner region separating the signal conductors; a ground layer disposed at a side of the second layer opposite from the first layer; plural dielectric layers separating the first layer, the second layer, and the ground layer.

Abstract: An electrical connector assembly includes a receptacle connector and a plug connector wherein the receptacle connector has an insulative housing with a plurality of contacts therein, and metallic shielding shell covering the housing. The housing includes a peripheral wall surrounding an island to form a mating cavity therebetween wherein the shielding shell covers the exterior surfaces of the peripheral wall and further provides pressing section upon an interior surfaces thereof. The plug connector has an insulative housing and a plurality of contacts therein, and a metallic shielding shell cover the housing. The housing forms a receiving cavity to receive the island. The shielding shell of the plug connector forms a recess in the outer abutting section to engage the pressing section of the receptacle connector during mating.

Abstract: An electrical connector includes: an insulative housing comprising a base portion defining a rearward surface and a tongue portion extending forwardly from the base portion; plural conductive terminals affixed to the insulative housing and each having a contacting portion exposed to the top and bottom surfaces of the tongue portion, a fixing portion embedded in the base portion, and a soldering portion extending backwardly out of the base portion; a shielding plate affixed to the insulative housing; a shielding shell covering the insulative housing and defining a sol space with the rearward surface of the base portion; and a waterproof sheet; wherein the base portion further comprises a stepped portion in the sol space, the waterproof sheet is formed by solidification of liquid insulative material flowing from the stepped portion to the rearward surface, and the waterproof sheet encloses the stepped portion.

Abstract: An electrical connector for soldering to a printed circuit board includes an insulative housing, a number of conductive terminals affixed to the insulative housing, and a metal shell surrounding the base portion. The insulative housing includes a base portion. Each conductive terminal includes a soldering portion extending laterally and outwardly from a lateral edge of the base portion. The metal shell includes a pair of longitudinal wall. The electrical connector includes an isolation block isolating the soldering portion from the longitudinal wall of the metal shell in a vertical direction.

Abstract: A card tray for an electronic device having a housing includes: a front door having an outer face and being adapted to be received in a slot opening of the housing; a rear tray portion configured to support an electronic card; and a bolt joining a rear end of the door and a front end of the tray portion together floatingly.

Abstract: A semiconductor device and method of manufacturing same are described. A first hafnium oxide (HfO2) layer is formed on a substrate. A titanium (Ti) layer is formed over the first hafnium oxide layer. A second hafnium oxide layer is formed over the titanium layer. The composite device structure is thermally annealed to produce a high-k dielectric structure having a hafnium titanium oxide (HfxTi1-xO2) layer interposed between the first hafnium oxide layer and the second hafnium oxide layer.

Abstract: A card connector assembly includes: an electrical connector (100) including a main body, plural contacts in the main body, and a tray guiding mechanism, the tray guiding mechanism including a slider (17), a pin member (19) coupled between the slider and the main body, a latch (20) moveable with the pin member, and an actuator; and a card tray (200) moveable together with the slider in the main body; wherein the actuator includes a bolt (16) slidably mounted in the main body, and the slider is moveable by the card tray to move the pin member and the latch against a biasing force to lock the latch to the bolt.

Abstract: A multi-layer circuit member includes: a first layer formed of a conductive material, the first layer including plural signal pads and a first reference plane spaced apart from the signal pads, the first reference plane including an outer region surrounding the signal pads and an inner region separating the plurality of signal pads; a second layer formed of a conductive material, the second layer including plural signal conductors and a second reference plane spaced apart from the signal conductors, the second reference plane including an outer region surrounding the signal conductors and an inner region separating the signal conductors; a ground layer disposed at a side of the second layer opposite from the first layer; plural dielectric layers separating the first layer, the second layer, and the ground layer.

Abstract: A semiconductor device and method of manufacturing same are described. A first hafnium oxide (HfO2) layer is formed on a substrate. A titanium (Ti) layer is formed over the first hafnium oxide layer. A second hafnium oxide layer is formed over the titanium layer. The composite device structure is thermally annealed to produce a high-k dielectric structure having a hafnium titanium oxide (HfxTi1-xO2) layer interposed between the first hafnium oxide layer and the second hafnium oxide layer.

Abstract: A card connector includes: an insulative housing (2) for receiving a card tray inserted in a front-to-back direction; and plural contacts (31) secured to the insulative housing, each contact including a frame portion (311), a curved portion connected inside the frame portion, and a tail portion (312) connected outside the frame portion, the curved portion including a first anchoring portion (315) and a second anchoring portion (315) respectively connected to the frame portion, a first arm (313) and a second arm (314) respectively continuing the first and second anchoring portions, a front connecting portion (317) and a rear connecting portion (318) respectively connected to the first and second arms, and a contacting portion (316) connected between the front and rear connecting portions.

Abstract: A card tray for an electronic device having a housing includes: a front door having an outer face and being adapted to be received in a slot opening of the housing; a rear tray portion configured to support an electronic card; and a bolt joining a rear end of the door and a front end of the tray portion together floatingly.