Patents by Inventor Chinyu SU
Chinyu SU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250120103Abstract: A method of forming a semiconductor device is disclosed. The method includes forming a plurality of isolation regions on a semiconductor substrate, forming a protective layer in a resistor region of the semiconductor substrate, after forming the protective layer, etching a gate dielectric layer to form first and second gate dielectric layers of a transistor in a transistor region of the semiconductor substrate, removing the protective layer, forming first and second dummy gate stacks over the first and second gate dielectric layers, respectively, forming a resistor in the resistor region, forming third and fourth dummy gate stacks over the resistor, and replacing each of the first, second, third, and fourth dummy gate stacks with a conductive material.Type: ApplicationFiled: December 9, 2024Publication date: April 10, 2025Inventors: Liang-Hsiang Chen, Chinyu Su, Che-Chih Hsu
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Patent number: 12205980Abstract: A method of forming a semiconductor device is disclosed. The method includes forming a plurality of isolation regions on a semiconductor substrate, forming a protective layer in a resistor region of the semiconductor substrate, after forming the protective layer, etching a gate dielectric layer to form first and second gate dielectric layers of a transistor in a transistor region of the semiconductor substrate, removing the protective layer, forming first and second dummy gate stacks over the first and second gate dielectric layers, respectively, forming a resistor in the resistor region, forming third and fourth dummy gate stacks over the resistor, and replacing each of the first, second, third, and fourth dummy gate stacks with a conductive material.Type: GrantFiled: May 20, 2022Date of Patent: January 21, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Liang-Hsiang Chen, Chinyu Su, Che-Chih Hsu
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Patent number: 12199033Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.Type: GrantFiled: March 7, 2023Date of Patent: January 14, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung Hsun Lin, Wei-Chun Hua, Wen-Chu Huang, Yen-Yu Chen, Che-Chih Hsu, Chinyu Su, Wen Han Hung
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Patent number: 12087627Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.Type: GrantFiled: July 21, 2022Date of Patent: September 10, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung Hsun Lin, Che-Chih Hsu, Wen-Chu Huang, Chinyu Su, Yen-Yu Chen, Wei-Chun Hua, Wen Han Hung
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Publication number: 20230378244Abstract: A method of forming a semiconductor device is disclosed. The method includes forming a plurality of isolation regions on a semiconductor substrate, forming a protective layer in a resistor region of the semiconductor substrate, after forming the protective layer, etching a gate dielectric layer to form first and second gate dielectric layers of a transistor in a transistor region of the semiconductor substrate, removing the protective layer, forming first and second dummy gate stacks over the first and second gate dielectric layers, respectively, forming a resistor in the resistor region, forming third and fourth dummy gate stacks over the resistor, and replacing each of the first, second, third, and fourth dummy gate stacks with a conductive material.Type: ApplicationFiled: May 20, 2022Publication date: November 23, 2023Inventors: Liang-Hsiang Chen, Chinyu Su, Che-Chih Hsu
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Publication number: 20230223335Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.Type: ApplicationFiled: March 7, 2023Publication date: July 13, 2023Inventors: Hung Hsun LIN, Wei-Chun HUA, Wen-Chu HUANG, Yen-Yu CHEN, Che-Chih HSU, Chinyu SU, Wen Han HUNG
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Patent number: 11616013Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.Type: GrantFiled: June 12, 2020Date of Patent: March 28, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung Hsun Lin, Che-Chih Hsu, Wen-Chu Huang, Chinyu Su, Yen-Yu Chen, Wei-Chun Hua, Wen Han Hung
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Publication number: 20220367343Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.Type: ApplicationFiled: July 21, 2022Publication date: November 17, 2022Inventors: Hung Hsun Lin, Che-Chih Hsu, Wen-Chu Huang, Chinyu Su, Yen-Yu Chen, Wei-Chun Hua, Wen Han Hung
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Patent number: 11393713Abstract: In a method of manufacturing a semiconductor device including a field effect transistor (FET), a sacrificial region is formed in a substrate, and a trench is formed in the substrate. A part of the sacrificial region is exposed in the trench. A space is formed by at least partially etching the sacrificial region, an isolation insulating layer is formed in the trench and the space, and a gate structure and a source/drain region are formed. An air spacer is formed in the space under the source/drain region.Type: GrantFiled: December 31, 2019Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Clement Hsinghen Wann, Chun Hsiung Tsai, Shahaji B. More, Che-Chih Hsu, Chinyu Su, Po-Han Tseng, Wen Han Hung, Chih-Hsin Ko, Yu-Ming Lin
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Publication number: 20210391251Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.Type: ApplicationFiled: June 12, 2020Publication date: December 16, 2021Inventors: Hung Hsun Lin, Che-Chih Hsu, Wen-Chu Huang, Chinyu Su, Yen-Yu Chen, Wei-Chun Hua, Wen Han Hung
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Publication number: 20200343127Abstract: In a method of manufacturing a semiconductor device including a field effect transistor (FET), a sacrificial region is formed in a substrate, and a trench is formed in the substrate. A part of the sacrificial region is exposed in the trench. A space is formed by at least partially etching the sacrificial region, an isolation insulating layer is formed in the trench and the space, and a gate structure and a source/drain region are formed. An air spacer is formed in the space under the source/drain region.Type: ApplicationFiled: December 31, 2019Publication date: October 29, 2020Inventors: Clement Hsingjen WANN, Chun Hsiung TSAI, Shahaji B. MORE, Che-Chih HSU, Chinyu SU, Po-Han TSENG, Wen Han HUNG