Patents by Inventor Chirag Chandrahas Shetty
Chirag Chandrahas Shetty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11881867Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.Type: GrantFiled: September 7, 2021Date of Patent: January 23, 2024Assignee: Texas Instruments IncorporatedInventors: Narasimhan Rajagopal, Eeshan Miglani, Chirag Chandrahas Shetty, Neeraj Shrivastava, Shagun Dusad, Srinivas Kumar Reddy Naru, Nithin Gopinath, Charls Babu, Shivam Srivastava, Viswanathan Nagarajan, Jagannathan Venkataraman, Harshit Moondra, Prasanth K, Visvesvaraya Appala Pentakota
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Patent number: 11438001Abstract: A method of using an analog-to-digital converter system includes receiving a sampled voltage corresponding to one of an input voltage and a known voltage, causing preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, causing a delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals, and adjusting one or more of the preamplifiers based on the digital signal. The disclosure also relates to a system which includes a voltage-to-delay frontend and a delay-resolving backend, and to a method which includes causing a delay comparator to generate a single-bit digital signal representing an order of receipt of input signals, causing the comparator to transmit a residue delay signal to a succeeding comparator, and transmitting a signal to adjust one or more of the preamplifiers based on the digital signal.Type: GrantFiled: December 24, 2020Date of Patent: September 6, 2022Assignee: Texas Instruments IncorporatedInventors: Narasimhan Rajagopal, Chirag Chandrahas Shetty, Neeraj Shrivastava, Prasanth K, Eeshan Miglani
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Patent number: 11424758Abstract: An analog-to-digital converter (ADC) having an input operable to receive an input voltage, VIN, and an output operable to output a digital code representative of VIN, the ADC including: a voltage-to-delay circuit having an input and an output, the input of the voltage-to-delay circuit coupled to the input of the ADC; a folding circuit having an input and an output, the input of the folding circuit coupled to the output of the voltage-to-delay circuit; and a time delay-based analog-to-digital converter backend having an input and a digital code output coupled to the output of the ADC, the input of the time delay-based analog-to-digital converter backend coupled to the output of the folding circuit.Type: GrantFiled: May 4, 2021Date of Patent: August 23, 2022Assignee: Texas Instruments IncorporatedInventors: Shagun Dusad, Chirag Chandrahas Shetty, Visvesvaraya Appala Pentakota
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Publication number: 20220247420Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.Type: ApplicationFiled: September 7, 2021Publication date: August 4, 2022Inventors: Narasimhan Rajagopal, Eeshan Miglani, Chirag Chandrahas Shetty, Neeraj Shrivastava, Shagun Dusad, Srinivas Kumar Reddy Naru, Nithin Gopinath, Charls Babu, Shivam Srivastava, Viswanathan Nagarajan, Jagannathan Venkataraman, Harshit Moondra, Prasanth K, Visvesvaraya Appala Pentakota
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Patent number: 11387840Abstract: A system for converting a voltage into output codes includes logic gates for processing delay signals based on earlier and later arriving signals generated by preamplifiers, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits of the codes, and an auxiliary delay comparator for generating an auxiliary digital signal for use in generating the output codes. A system may include logic gates for generating delay signals based on earlier and later arriving signals, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits, and a multiplexer system for transmitting a selected one of the residue signals.Type: GrantFiled: December 21, 2020Date of Patent: July 12, 2022Assignee: Texas Instruments IncorporatedInventors: Eeshan Miglani, Visvesvaraya Appala Pentakota, Chirag Chandrahas Shetty
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Publication number: 20220209782Abstract: A method of using an analog-to-digital converter system includes receiving a sampled voltage corresponding to one of an input voltage and a known voltage, causing preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, causing a delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals, and adjusting one or more of the preamplifiers based on the digital signal. The disclosure also relates to a system which includes a voltage-to-delay frontend and a delay-resolving backend, and to a method which includes causing a delay comparator to generate a single-bit digital signal representing an order of receipt of input signals, causing the comparator to transmit a residue delay signal to a succeeding comparator, and transmitting a signal to adjust one or more of the preamplifiers based on the digital signal.Type: ApplicationFiled: December 24, 2020Publication date: June 30, 2022Inventors: Narasimhan RAJAGOPAL, Chirag Chandrahas SHETTY, Neeraj SHRIVASTAVA, Prasanth K, Eeshan MIGLANI
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Publication number: 20220200620Abstract: A system for converting a voltage into output codes includes logic gates for processing delay signals based on earlier and later arriving signals generated by preamplifiers, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits of the codes, and an auxiliary delay comparator for generating an auxiliary digital signal for use in generating the output codes. A system may include logic gates for generating delay signals based on earlier and later arriving signals, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits, and a multiplexer system for transmitting a selected one of the residue signals.Type: ApplicationFiled: December 21, 2020Publication date: June 23, 2022Inventors: Eeshan MIGLANI, Visvesvaraya Appala PENTAKOTA, Chirag Chandrahas SHETTY
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Patent number: 11316525Abstract: An analog-to-digital converter system includes a digital-to-analog converter for generating calibration voltages based on digital input codes, and an analog-to-digital converter, connected to the digital-to-analog converter, for receiving the calibration voltages from the digital-to-analog converter, for receiving sampled voltages, for generating digital output codes based on the calibration voltages, and for generating digital output codes based on the sampled voltages. The analog-to-digital converter system may have a lookup table, connected to the analog-to-digital converter, for storing the first digital output codes in association with the digital input codes. A method of calibrating an analog-to-digital converter system is also disclosed.Type: GrantFiled: January 26, 2021Date of Patent: April 26, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Visvesvaraya Appala Pentakota, Narasimhan Rajagopal, Chirag Chandrahas Shetty, Prasanth K, Neeraj Shrivastava, Eeshan Miglani, Jagannathan Venkataraman
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Publication number: 20210258018Abstract: An analog-to-digital converter (ADC) having an input operable to receive an input voltage, VIN, and an output operable to output a digital code representative of VIN, the ADC including: a voltage-to-delay circuit having an input and an output, the input of the voltage-to-delay circuit coupled to the input of the ADC; a folding circuit having an input and an output, the input of the folding circuit coupled to the output of the voltage-to-delay circuit; and a time delay-based analog-to-digital converter backend having an input and a digital code output coupled to the output of the ADC, the input of the time delay-based analog-to-digital converter backend coupled to the output of the folding circuit.Type: ApplicationFiled: May 4, 2021Publication date: August 19, 2021Inventors: Shagun DUSAD, Chirag Chandrahas SHETTY, Visvesvaraya Appala PENTAKOTA
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Patent number: 11031947Abstract: An RF receiver including: a low noise amplifier adapted to be coupled to an antenna and having an output; a bandpass filter coupled to the output of the low noise amplifier and having a voltage signal output, VIN; a conversion and folding circuit; and an analog-to-digital converter for converting the earlier-arriving or later-arriving delay signals into a digital code representing the voltage signal. The conversion and folding circuit including: a voltage-to-delay converter block, including preamplifiers, for converting the voltage signal into delay signals; and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals.Type: GrantFiled: April 28, 2020Date of Patent: June 8, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shagun Dusad, Chirag Chandrahas Shetty, Visvesvaraya Appala Pentakota
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Patent number: 10903845Abstract: A clock-less delay comparator coupled to a first input signal and a second input signal, the clock-less delay comparator comprising: a first transistor having a control terminal coupled to the second input signal, a first current terminal coupled to a first voltage supply, and a second current terminal; a second transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a third transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fourth transistor having a control terminal coupled to the first input signal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fifth transistor having a control terminal coupled to the second input signal, a first current terminal, and a second current terminal coupled to the control terminal of the third transistor; a sixth transistor having a control terminal coupled to the first inputType: GrantFiled: July 29, 2020Date of Patent: January 26, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Visvesvaraya Appala Pentakota, Rishi Soundararajan, Shagun Dusad, Chirag Chandrahas Shetty
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Publication number: 20200358450Abstract: A clock-less delay comparator coupled to a first input signal and a second input signal, the clock-less delay comparator comprising: a first transistor having a control terminal coupled to the second input signal, a first current terminal coupled to a first voltage supply, and a second current terminal; a second transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a third transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fourth transistor having a control terminal coupled to the first input signal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fifth transistor having a control terminal coupled to the second input signal, a first current terminal, and a second current terminal coupled to the control terminal of the third transistor; a sixth transistor having a control terminal coupled to the first inputType: ApplicationFiled: July 29, 2020Publication date: November 12, 2020Inventors: Visvesvaraya Appala PENTAKOTA, Rishi SOUNDARARAJAN, Shagun DUSAD, Chirag Chandrahas SHETTY
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Patent number: 10778243Abstract: An analog-to-digital converter, comprising: a voltage to delay circuit having a voltage input, a threshold voltage input, a first output and a second output, wherein a leading edge of the first output is delayed, by a first delay magnitude, in relationship to a leading edge of the second output; and a first stage including: a first logic gate having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, and an output; and a first stage delay comparator having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, a sign signal output and a first stage delay comparator output, wherein the sign signal output represents whether the voltage input is greater than or less than the threshold voltage input.Type: GrantFiled: April 28, 2020Date of Patent: September 15, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Visvesvaraya Appala Pentakota, Rishi Soundararajan, Shagun Dusad, Chirag Chandrahas Shetty
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Publication number: 20200259501Abstract: An analog-to-digital converter, comprising: a voltage to delay circuit having a voltage input, a threshold voltage input, a first output and a second output, wherein a leading edge of the first output is delayed, by a first delay magnitude, in relationship to a leading edge of the second output; and a first stage including: a first logic gate having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, and an output; and a first stage delay comparator having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, a sign signal output and a first stage delay comparator output, wherein the sign signal output represents whether the voltage input is greater than or less than the threshold voltage input.Type: ApplicationFiled: April 28, 2020Publication date: August 13, 2020Inventors: Visvesvaraya Appala PENTAKOTA, Rishi SOUNDARARAJAN, Shagun DUSAD, Chirag Chandrahas SHETTY
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Publication number: 20200259502Abstract: An RF receiver including: an antenna cable of receiving an RF signal; a low noise amplifier coupled to the antenna and having an output; a bandpass filter coupled to the output of the low noise amplifier and having a voltage signal output, VIN; a conversion and folding circuit; and an analog-to-digital converter for converting the earlier-arriving or later-arriving delay signals into a digital code representing the voltage signal.Type: ApplicationFiled: April 28, 2020Publication date: August 13, 2020Inventors: Shagun DUSAD, Chirag Chandrahas SHETTY, Visvesvaraya Appala PENTAKOTA
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Patent number: 10673453Abstract: An analog-to-digital converter has a logic gate for generating an output signal having a delay corresponding to a delay between input signals. The logic gate includes inputs for receiving the input signals, and an output for outputting the output signal. A delay comparator generates a digital signal representative of the order of the input signals, and generates a delay signal having a delay corresponding to the delay between the input signals. The delay comparator has inputs for receiving the input signals, a digital output for outputting the digital signal, and a delay output for outputting the delay signal. A delay-based analog-to-digital converter, with a front stage and successive residual stages, is also disclosed. A delay comparator having merged comparator, sign-out, and delay-out circuits, and which may be operated within one of successive stages, without a clock, is also disclosed.Type: GrantFiled: July 22, 2019Date of Patent: June 2, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Visvesvaraya Appala Pentakota, Rishi Soundararajan, Shagun Dusad, Chirag Chandrahas Shetty
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Patent number: 10673456Abstract: A conversion and folding circuit includes a voltage-to-delay converter block, including preamplifiers, for converting a voltage signal into delay signals, and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals. If desired, the logic gates may include odd and even chains for outputting delay signals to first and second analog-to-digital converters. If desired, the conversion and folding circuit may include first and second chains, and a chain selection circuit for selectively outputting a delay signal from a desired one of the first and second chains.Type: GrantFiled: May 13, 2019Date of Patent: June 2, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shagun Dusad, Chirag Chandrahas Shetty, Visvesvaraya Appala Pentakota