Abstract: A method includes: receiving an integrated circuit design; obtaining a timing path between a first sequential circuit element at a launch end of the timing path and a second sequential circuit element at a capture end of the timing path of the integrated circuit design; determining, by a processing device, a common clock that drives a first clock clocking the first sequential circuit element and a second clock clocking the second sequential circuit element based on a clock graph of relationships between a plurality of clocks of the integrated circuit design; and setting a timing constraint for the timing path of the integrated circuit design based on a period of the common clock.

Abstract: A wastewater refinery comprising one or more electrodialytic cells with mono-, di-, or multi-valent selective membranes interspersed with one or more concentrate compartments to selectively recovery ions from wastewater. The wastewater refinery may harvest ions by utilising techniques including ion selective resins and pervaporation.