Patents by Inventor Chirag Sharma

Chirag Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210125159
    Abstract: Systems, devices and methods may provide for facilitating a direct fund transfer from an aid organization to a service provider. The system may maintain an aid organization account associated with the aid organization, maintain a beneficiary account associated with each beneficiary enrolled with the aid organization, and maintain a service provider account associated with each service provider. Each beneficiary account may be configured as a virtual stored-value account for storing value corresponding to funds from the aid organization. The system may also receive transaction data corresponding to a transaction between a beneficiary and a service provider including identifier information, debit a value corresponding to the transaction amount from the beneficiary account that is mapped to a beneficiary identifier, and transfer funds corresponding to the transaction amount from the aid organization account directly to a service provider account that is mapped to a service provider identifier.
    Type: Application
    Filed: October 23, 2019
    Publication date: April 29, 2021
    Applicant: MASTERCARD INTERNATIONAL INCORPORATED
    Inventors: Paul Michael Musser, Penelope Psarros, Ali Khalaf, Yara Hattab, Chirag Sharma, Mohammad Al-Hussein
  • Patent number: 7548071
    Abstract: A technique for reflectometry testing of a signal path is disclosed. The technique includes injecting a test signal based on a probe pseudo-noise sequence into the signal path and obtaining a response signal. A sliding reference pseudo-noise sequence is correlated against the response signal. Both the probe sequence and the reference sequence are generated at a chip rate. The correlation is obtained for integer chip time delays, and sub-chip resolution of a peak correlation delay is estimated from at least two samples of the correlation.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: June 16, 2009
    Assignee: University of Utah Research Foundation
    Inventors: Reid Harrison, Cynthia Furse, Chirag Sharma
  • Publication number: 20070194796
    Abstract: A technique for reflectometry testing of a signal path is disclosed. The technique includes injecting a test signal based on a probe pseudo-noise sequence into the signal path and obtaining a response signal. A sliding reference pseudo-noise sequence is correlated against the response signal. Both the probe sequence and the reference sequence are generated at a chip rate. The correlation is obtained for integer chip time delays, and sub-chip resolution of a peak correlation delay is estimated from at least two samples of the correlation.
    Type: Application
    Filed: January 30, 2007
    Publication date: August 23, 2007
    Inventors: Reid Harrison, Cynthia Furse, Chirag Sharma
  • Publication number: 20050008071
    Abstract: A multiplierless IIR filter incorporates power-of-two coefficients to perform shift operations to reduce space and increase speed. To optimize performance, a genetic algorithm generates the power-of-two coefficients. The filter architecture includes shift registers to receive input samples and previous outputs. A shifter stage is employed to perform shift operations for the input samples and previous outputs based on corresponding power-of-two coefficients. Products are added by parallelism and sequential pipelining to produce an output.
    Type: Application
    Filed: July 8, 2003
    Publication date: January 13, 2005
    Inventors: Tamal Bose, Alan Shaw, Chirag Sharma, Ratchaneekorn Thamvichai