Patents by Inventor Chiranjeev Acharya

Chiranjeev Acharya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10810146
    Abstract: Routing circuitry 400 is provided for routing transaction requests to a selected destination node. The routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Request regulators 401, 402, 403 are provided to monitor resource usage for read, atomic and write requests, and issue circuitry 431 controls the issuing of a transaction request received from a requesting node, in dependence on resource usage monitoring performed by the request regulators. The issue circuitry controls the issuing of atomic requests in dependence on the resource usage monitored by the write request regulator and the resource usage monitored by the atomic request regulator.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 20, 2020
    Assignee: ARM LIMITED
    Inventors: Arthur Brian Laughton, Chiranjeev Acharya, Eduard Vardanyan
  • Patent number: 10740032
    Abstract: Data access routing circuitry 4, 6 is provided for routing data access request to a selected destination node. The data access routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Resource allocation circuitry 70, 71 is provided to control allocation of resource for handling data access requests which require a read response. The resource allocation circuitry 70, 71 reserves resource for handling the at least one type of atomic data access request and prevents use of the reserved resource 76 for handling read requests.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: August 11, 2020
    Assignee: Arm Limited
    Inventors: Chiranjeev Acharya, Sean James Salisbury, Eduard Vardanyan, Arthur Brian Laughton
  • Patent number: 10437750
    Abstract: An interconnect for providing data access between nodes of an integrated circuit, comprises a predetermined type of ingress port comprising routing circuitry responsive to a read-triggering request received from a requesting node to select from a selected egress port via which signals are to be routed to a destination node to control the destination node to return at least one read response dependent on data read from a target storage location. In response to the read-triggering request, the routing circuitry obtains a relative data width indication specifying whether read responses received at the selected egress port have a narrower data width than read responses to be provided to the requesting node by the predetermined type of ingress port, and controls allocation of resource for handling the read-triggering request or the at least one read response depending on the relative data width indication.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 8, 2019
    Assignee: ARM Limited
    Inventors: Arthur Brian Laughton, Sean James Salisbury, Chiranjeev Acharya, Eduard Vardanyan
  • Publication number: 20190196990
    Abstract: An interconnect for providing data access between nodes of an integrated circuit, comprises a predetermined type of ingress port comprising routing circuitry responsive to a read-triggering request received from a requesting node to select from a selected egress port via which signals are to be routed to a destination node to control the destination node to return at least one read response dependent on data read from a target storage location. In response to the read-triggering request, the routing circuitry obtains a relative data width indication specifying whether read responses received at the selected egress port have a narrower data width than read responses to be provided to the requesting node by the predetermined type of ingress port, and controls allocation of resource for handling the read-triggering request or the at least one read response depending on the relative data width indication.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Arthur Brian LAUGHTON, Sean James SALISBURY, Chiranjeev ACHARYA, Eduard VARDANYAN
  • Publication number: 20190179783
    Abstract: Routing circuitry 400 is provided for routing transaction requests to a selected destination node. The routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Request regulators 401, 402, 403 are provided to monitor resource usage for read, atomic and write requests, and issue circuitry 431 controls the issuing of a transaction request received from a requesting node, in dependence on resource usage monitoring performed by the request regulators. The issue circuitry controls the issuing of atomic requests in dependence on the resource usage monitored by the write request regulator and the resource usage monitored by the atomic request regulator.
    Type: Application
    Filed: November 26, 2018
    Publication date: June 13, 2019
    Inventors: Arthur Brian LAUGHTON, Chiranjeev ACHARYA, Eduard VARDANYAN
  • Publication number: 20190163400
    Abstract: Data access routing circuitry 4, 6 is provided for routing data access request to a selected destination node. The data access routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Resource allocation circuitry 70, 71 is provided to control allocation of resource for handling data access requests which require a read response. The resource allocation circuitry 70, 71 reserves resource for handling the at least one type of atomic data access request and prevents use of the reserved resource 76 for handling read requests.
    Type: Application
    Filed: October 1, 2018
    Publication date: May 30, 2019
    Inventors: Chiranjeev ACHARYA, Sean James SALISBURY, Eduard VARDANYAN, Arthur Brian LAUGHTON
  • Patent number: 10255103
    Abstract: Transaction handling apparatus comprises a response buffer; and tracking circuitry to store data defining each transaction issued by one or more transaction master devices and to control routing of a transaction response to a given transaction either to the response buffer or as an output to the transaction master device which issued the given transaction; the response buffer being configured to access an indicator for each buffered transaction response indicating whether a response has been output by the apparatus for a previously issued transaction, on which that buffered transaction response depends, and to output the buffered transaction response to the transaction master device which issued that transaction when the previously issued transaction has already been output by the apparatus.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: April 9, 2019
    Assignee: ARM Limited
    Inventors: Chiranjeev Acharya, Arthur Brian Laughton, Sean James Salisbury
  • Publication number: 20180285145
    Abstract: Transaction handling apparatus comprises a response buffer; and tracking circuitry to store data defining each transaction issued by one or more transaction master devices and to control routing of a transaction response to a given transaction either to the response buffer or as an output to the transaction master device which issued the given transaction; the response buffer being configured to access an indicator for each buffered transaction response indicating whether a response has been output by the apparatus for a previously issued transaction, on which that buffered transaction response depends, and to output the buffered transaction response to the transaction master device which issued that transaction when the previously issued transaction has already been output by the apparatus.
    Type: Application
    Filed: April 4, 2017
    Publication date: October 4, 2018
    Inventors: Chiranjeev ACHARYA, Arthur Brian LAUGHTON, Sean James SALISBURY
  • Patent number: 7949907
    Abstract: A programmable logic device is presented. The device comprises a plurality of logic elements and a plurality of I/O pins; a multiplexer and/or a de-multiplexer unit. The multiplexer and/or multiplexer unit is coupled between said logic elements and I/O pins. The device further comprises a control unit for generating control signal/s for selecting one of the inputs of the multiplexer and/or one of the outputs of the de-multiplexer. The control unit includes inputs for receiving a first clock signal, a second clock signal and indicators, said indicators being indicative of a phase skew relation amongst the clock signals. The control unit being configured for generating adaptively adjusted control signal/s according to the clock signals and indicators, said control signal/s are adaptively adjusted for eliminating impact of the phase skew amongst the clock signals.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: May 24, 2011
    Assignee: Wipro Limited
    Inventors: Vijay Kumar Kodavalla, Chiranjeev Acharya
  • Publication number: 20080092001
    Abstract: A programmable logic device is presented. The device comprises a plurality of logic elements and a plurality of I/O pins; a multiplexer and/or a de-multiplexer unit. The multiplexer and/or multiplexer unit is coupled between said logic elements and I/O pins. The device further comprises a control unit for generating control signal/s for selecting one of the inputs of the multiplexer and/or one of the outputs of the de-multiplexer. The control unit includes inputs for receiving a first clock signal, a second clock signal and indicators, said indicators being indicative of a phase skew relation amongst the clock signals. The control unit being configured for generating adaptively adjusted control signals according to the clock signals and indicators, said control signal's are adaptively adjusted for eliminating impact of the phase skew amongst the clock signals.
    Type: Application
    Filed: October 3, 2006
    Publication date: April 17, 2008
    Inventors: Vijay Kumar Kodavalla, Chiranjeev Acharya