Patents by Inventor Chiranjeevi Sirandas

Chiranjeevi Sirandas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Descriptor fetching for a multi-queue direct memory access system
    Patent number: 12259833
    Abstract: Descriptor fetch for a direct memory access system includes obtaining a descriptor for processing a received data packet. A determination is made as to whether the descriptor is a head descriptor of a chain descriptor. In response to determining that the descriptor is a head descriptor, one or more tail descriptors are fetched from a descriptor table specified by the head descriptor. A number of the tail descriptors fetched is determined based on a running count of a buffer size of the chain descriptor determined as each tail descriptor is fetched compared to a size of the data packet.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: March 25, 2025
    Assignee: XILINX, INC.
    Inventors: Chandrasekhar S. Thyamagondlu, Tao Yu, Chiranjeevi Sirandas, Nicholas Trank
  • VARIABLE BUFFER SIZE DESCRIPTOR FETCHING FOR A MULTI-QUEUE DIRECT MEMORY ACCESS SYSTEM
    Publication number: 20240330213
    Abstract: Descriptor fetch for a direct memory access system includes, in response to receiving a first data packet, fetching a plurality of descriptors including a first descriptor and a specified number of prefetched descriptors. The plurality of descriptors specify different buffer sizes. In response to processing each data packet, selectively replenishing the plurality of fetched descriptors to the specified number of prefetched descriptors.
    Type: Application
    Filed: March 28, 2023
    Publication date: October 3, 2024
    Applicant: Xilinx, Inc.
    Inventors: Chandrasekhar S. Thyamagondlu, Tao Yu, Chiranjeevi Sirandas, Nicholas Trank
  • DESCRIPTOR FETCHING FOR A MULTI-QUEUE DIRECT MEMORY ACCESS SYSTEM
    Publication number: 20240330215
    Abstract: Descriptor fetch for a direct memory access system includes obtaining a descriptor for processing a received data packet. A determination is made as to whether the descriptor is a head descriptor of a chain descriptor. In response to determining that the descriptor is a head descriptor, one or more tail descriptors are fetched from a descriptor table specified by the head descriptor. A number of the tail descriptors fetched is determined based on a running count of a buffer size of the chain descriptor determined as each tail descriptor is fetched compared to a size of the data packet.
    Type: Application
    Filed: March 28, 2023
    Publication date: October 3, 2024
    Applicant: Xilinx, Inc.
    Inventors: Chandrasekhar S. Thyamagondlu, Tao Yu, Chiranjeevi Sirandas, Nicholas Trank