Abstract: This application discloses a video recording apparatus and a video recording method. The video recording apparatus includes a first demultiplexer, configured to: separate program information, audio data, and video data from a transport stream; a marker, configured to: mark the separated audio data and the separated video data, and transmit a mixed stream to an encryption processor, where the mixed stream includes the program information, the marked audio data, and the marked video data; and the encryption processor, configured to: identify the marked audio data and the marked video data in the mixed stream, encrypt the identified audio data and the identified video data to obtain encrypted audio data and encrypted video data, and transmit the encrypted audio data, the encrypted video data, and the program information to a memory in a rich execution environment REE for storage, so as to implement video recording.

Abstract: This application discloses a video recording apparatus and a video recording method. The video recording apparatus includes a first demultiplexer, configured to: separate program information, audio data, and video data from a transport stream; a marker, configured to: mark the separated audio data and the separated video data, and transmit a mixed stream to an encryption processor, where the mixed stream includes the program information, the marked audio data, and the marked video data; and the encryption processor, configured to: identify the marked audio data and the marked video data in the mixed stream, encrypt the identified audio data and the identified video data to obtain encrypted audio data and encrypted video data, and transmit the encrypted audio data, the encrypted video data, and the program information to a memory in a rich execution environment REE for storage, so as to implement video recording.

Abstract: A method and an apparatus for controlling video output, where the method includes detecting in real time, by a security controller, whether an output resolution configured in a video display controller and a high-bandwidth digital content protection (HDCP) encryption status configured in a high-definition multimedia interface (HDMI) satisfy an HDCP requirement of a video, and when the HDCP requirement of the video is not satisfied, sending, by the security controller, an instruction to the video display controller instructing the video display controller to stop outputting the video. Hence, when the HDCP requirement of the video is not satisfied the output video is insecure such that the security controller sends the instruction to the video display controller instructing the video display controller to stop outputting the video. Therefore, security of the video output is ensured.

Abstract: A method and an apparatus for controlling video output, where the method includes detecting in real time, by a security controller, whether an output resolution configured in a video display controller and a high-bandwidth digital content protection (HDCP) encryption status configured in a high-definition multimedia interface (HDMI) satisfy an HDCP requirement of a video, and when the HDCP requirement of the video is not satisfied, sending, by the security controller, an instruction to the video display controller instructing the video display controller to stop outputting the video. Hence, when the HDCP requirement of the video is not satisfied the output video is insecure such that the security controller sends the instruction to the video display controller instructing the video display controller to stop outputting the video. Therefore, security of the video output is ensured.

Abstract: A system for clock recovery in digital video communication includes a delay measurement block for generating PCR input signals and for continuously determining the time interval between successive PCR input signals. The system also includes a first storage device for generating a first PCR signal corresponding to the time interval between arrival of successive PCR input signals and a PCR inter-arrival time computation filtering device to determine the average time of arrival difference between successive PCR packets. The system further includes an error correction device for minimizing error in the average PCR difference between successive PCR packets, a controlled system clock generator coupled to the output of the error correction device to generate system clock, a second storage device for generating a first system clock output, and a controlled clock period difference computation element for computing the clock period difference between the first and second system clock outputs.

Abstract: A system for clock recovery in digital video communication includes a delay measurement block for generating PCR input signals and for continuously determining the time interval between successive PCR input signals. The system also includes a first storage device for generating a first PCR signal corresponding to the time interval between arrival of successive PCR input signals and a PCR inter-arrival time computation filtering device to determine the average time of arrival difference between successive PCR packets. The system further includes an error correction device for minimizing error in the average PCR difference between successive PCR packets, a controlled system clock generator coupled to the output of the error correction device to generate system clock, a second storage device for generating a first system clock output, and a controlled clock period difference computation element for computing the clock period difference between the first and second system clock outputs.