Patents by Inventor Chirayarikathuveedu Premachandran Sankarapillai

Chirayarikathuveedu Premachandran Sankarapillai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7381629
    Abstract: A substrate having target transfer regions thereon is provided. A sacrificial wafer is coated with a polymer layer with low adhesion to metals. A conductive layer is coated on the polymer layer and covered with a photoresist layer which is patterned to provide openings to the conductive layer. Thin film and passive or active device structures are formed on the conductive layer within the openings. The substrate is bonded to the sacrificial wafer wherein the thin film and passive or active device structures and the photoresist layer provide the bonding and wherein the thin film and passive or active device structures contact the substrate at the target transfer regions. The photoresist is stripped in a high frequency agitation bath wherein the photoresist separates from the sacrificial wafer and wherein the thin film and passive or active device structures separate from the polymer layer to complete transfer bonding.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: June 3, 2008
    Assignee: Agency for Science, Technology and Research
    Inventors: Chirayarikathuveedu Premachandran Sankarapillai, Ranganathan Nagarajan, Mohanraj Soundarapandian
  • Patent number: 7326629
    Abstract: This invention describes a method of stacking, bonding, and electrically interconnecting a plurality of thin integrated circuit wafers to form an interconnected stack of integrated circuit layers. The first integrated circuit layer is formed by conventional processing on a silicon wafer to the stage where bond pads are patterned on a wiring layer interconnecting the subjacent semiconductive devices. The remaining integrated circuit layers are formed by first processing a standard wafer to form integrated circuit devices and wiring levels up to but not including bond pads. Each of these wafers is mounted onto a handler wafer by its upper face with a sacrificial bonding agent. The wafer is thinned, permanently fastened to the top surface of the first base wafer by a non-conductive adhesive applied to the thinned under face, and dismounted from the handler. Vertical openings are etched through the thinned layer to the bond pads on the subjacent wafer.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: February 5, 2008
    Assignee: Agency for Science, Technology and Research
    Inventors: Ranganathan Nagarajan, Chirayarikathuveedu Premachandran Sankarapillai
  • Patent number: 7183176
    Abstract: A wafer is provided having through-holes therein to form a through-hole via wafer. A substrate of a sacrificial wafer is provided. The substrate is coated with a polymer having low adhesion to metals. A conductive layer is deposited on the polymer. A photoresist layer is coated on the conductive layer. The through-hole via wafer is bonded to the sacrificial wafer wherein the photoresist layer provides the bonding. The photoresist exposed in the through-holes is developed away to expose the conductive layer. The through-holes are filled with a conductive material by electroplating the conductive layer. The photoresist is stripped in an ultrasonic bath wherein the photoresist separates from the through-hole wafer and wherein the filled through-holes separate from the polymer at an interface between the polymer and the conductive layer to complete separation of the through-hole via wafer from the sacrificial wafer.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: February 27, 2007
    Assignee: Agency for Science, Technology and Research
    Inventors: Chirayarikathuveedu Premachandran Sankarapillai, Ranganathan Nagarajan, Mohanraj Soundarapandian