Patents by Inventor Chirayarikathuveedu Sankarapillai
Chirayarikathuveedu Sankarapillai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9272899Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.Type: GrantFiled: January 7, 2015Date of Patent: March 1, 2016Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Rama Krishna Kotlanka, Rakesh Kumar, Premachandran Chirayarikathuveedu Sankarapillai, Huamao Lin, Pradeep Yelehanka
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Publication number: 20150115453Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.Type: ApplicationFiled: January 7, 2015Publication date: April 30, 2015Inventors: Rama Krishna KOTLANKA, Rakesh KUMAR, Premachandran CHIRAYARIKATHUVEEDU SANKARAPILLAI, Huamao LIN, Pradeep YELEHANKA
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Patent number: 8940616Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.Type: GrantFiled: July 27, 2012Date of Patent: January 27, 2015Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Rama Krishna Kotlanka, Rakesh Kumar, Premachandran Chirayarikathuveedu Sankarapillai, Huamao Lin, Pradeep Yelehanka
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Publication number: 20140030847Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.Type: ApplicationFiled: July 27, 2012Publication date: January 30, 2014Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Rama Krishna KOTLANKA, Rakesh KUMAR, Premachandran CHIRAYARIKATHUVEEDU SANKARAPILLAI, Huamao LIN, Pradeep YELEHANKA
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Patent number: 8513767Abstract: A method for forming a device is disclosed. A support substrate having first and second major surfaces is provided. An interconnect is formed through the first and second major surfaces in the support substrate. The interconnect has first and second portions. The first portion extends from one of the first or second major surfaces and the second portion extends from the other of the first and second major surfaces. The interconnect includes a partial via plug having a conductive material in a first portion of the interconnect. The via plug has a bottom at about an interface of the first and second portions. The second portion of the interconnect is heavily doped with dopants of a first polarity type.Type: GrantFiled: March 21, 2011Date of Patent: August 20, 2013Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Rama Krishna Kotlanka, Rakesh Kumar, Premachandran Chirayarikathuveedu Sankarapillai, Pradeep Ramachandramurthy Yelehanka
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Publication number: 20120241901Abstract: A method for forming a device is disclosed. A support substrate having first and second major surfaces is provided. An interconnect is formed through the first and second major surfaces in the support substrate. The interconnect has first and second portions. The first portion extends from one of the first or second major surfaces and the second portion extends from the other of the first and second major surfaces. The interconnect includes a partial via plug having a conductive material in a first portion of the interconnect. The via plug has a bottom at about an interface of the first and second portions. The second portion of the interconnect is heavily doped with dopants of a first polarity type.Type: ApplicationFiled: March 21, 2011Publication date: September 27, 2012Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Rama Krishna KOTLANKA, Rakesh KUMAR, Premachandran CHIRAYARIKATHUVEEDU SANKARAPILLAI, Pradeep Ramachandramurthy YELEHANKA
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Patent number: 8127794Abstract: A dispenser arrangement for fluidic dispensing control into a microfluidic component comprising an enclosed fluid holding area having a base portion and a top portion and a valve adapted to be movable between an open position and a closed position and positioned at least partially in the fluid holding area. The valve comprises an elongated hollow portion having a body and two ends adapted for fluid flow from the fluid holding area to the microfluidic component in the open position, a first opening on the body of the hollow portion positioned within the fluid holding area allowing fluid communication from the fluid holding area to the microfluidic component in the open position, a sealing portion connected to a first end of the hollow portion positioned within the fluid holding area adapted for sealing connection with the top portion of the fluid holding area in the closed position and a slant second opening at a second end of the hollow portion positioned outside of the fluid holding area.Type: GrantFiled: September 19, 2006Date of Patent: March 6, 2012Assignee: Agency for Science, Technology and ResearchInventors: Ling Xie, Chirayarikathuveedu Sankarapillai Premachandran, Ser Choong Chong
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Publication number: 20100084032Abstract: A dispenser arrangement for fluidic dispensing control into a microfluidic component comprising an enclosed fluid holding area having a base portion and a top portion and a valve adapted to be movable between an open position and a closed position and positioned at least partially in the fluid holding area. The valve comprises an elongated hollow portion having a body and two ends adapted for fluid flow from the fluid holding area to the microfluidic component in the open position, a first opening on the body of the hollow portion positioned within the fluid holding area allowing fluid communication from the fluid holding area to the microfluidic component in the open position, a sealing portion connected to a first end of the hollow portion positioned within the fluid holding area adapted for sealing connection with the top portion of the fluid holding area in the closed position and a slant second opening at a second end of the hollow portion positioned outside of the fluid holding area.Type: ApplicationFiled: September 19, 2006Publication date: April 8, 2010Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventors: Ling Xie, Chirayarikathuveedu Sankarapillai Premachandran, Ser Choong Chong
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Patent number: 7616987Abstract: A microprobe that is capable of using an incident and reflected radiation ray for three-dimensional (3-D) bio-imaging. The microprobe comprises a hollow body closed at one end and having an aperture at an opposite end, at least one 3-D free space micromirror, at least one focusing lens, and a beam director or a beam coupler or other kind of device for beam coupling or splitting. The beam director is arranged at the aperture end of the hollow body and is adapted to direct the incident ray into the hollow body via the aperture. Within said hollow body is the at least one focusing lens and the at least one micromirror arranged respectively from the aperture, such that the distance between the focusing lens and the micromirror allows for the incident light ray to be directed onto the micromirror.Type: GrantFiled: October 5, 2005Date of Patent: November 10, 2009Assignees: Agency For Science, Technology and Research, National University of SingaporeInventors: Chirayarikathuveedu Sankarapillai Premachandran, Janak Singh, Joseph Suresh Paul, Pamidighantam Venkata Ramana, Colin James Richard Sheppard
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Publication number: 20070141804Abstract: A substrate having target transfer regions thereon is provided. A sacrificial wafer is coated with a polymer layer with low adhesion to metals. A conductive layer is coated on the polymer layer and covered with a photoresist layer which is patterned to provide openings to the conductive layer. Thin film and passive or active device structures are formed on the conductive layer within the openings. The substrate is bonded to the sacrificial wafer wherein the thin film and passive or active device structures and the photoresist layer provide the bonding and wherein the thin film and passive or active device structures contact the substrate at the target transfer regions. The photoresist is stripped in a high frequency agitation bath wherein the photoresist separates from the sacrificial wafer and wherein the thin film and passive or active device structures separate from the polymer layer to complete transfer bonding.Type: ApplicationFiled: February 12, 2007Publication date: June 21, 2007Inventors: Chirayarikathuveedu Sankarapillai, Ranganathan Nagarajan, Mohanraj Soundarapandian
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Publication number: 20060057836Abstract: This invention describes a method of stacking, bonding, and electrically interconnecting a plurality of thin integrated circuit wafers to form an interconnected stack of integrated circuit layers. The first integrated circuit layer is formed by conventional processing on a silicon wafer to the stage where bond pads are patterned on a wiring layer interconnecting the subjacent semiconductive devices. The remaining integrated circuit layers are formed by first processing a standard wafer to form integrated circuit devices and wiring levels up to but not including bond pads. Each of these wafers is mounted onto a handler wafer by its upper face with a sacrificial bonding agent. The wafer is thinned, permanently fastened to the top surface of the first base wafer by a non-conductive adhesive applied to the thinned under face, and dismounted from the handler. Vertical openings are etched through the thinned layer to the bond pads on the subjacent wafer.Type: ApplicationFiled: June 29, 2005Publication date: March 16, 2006Inventors: Ranganathan Nagarajan, Chirayarikathuveedu Sankarapillai
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Publication number: 20060046432Abstract: A wafer is provided having through-holes therein to form a through-hole via wafer. A substrate of a sacrificial wafer is provided. The substrate is coated with a polymer having low adhesion to metals. A conductive layer is deposited on the polymer. A photoresist layer is coated on the conductive layer. The through-hole via wafer is bonded to the sacrificial wafer wherein the photoresist layer provides the bonding. The photoresist exposed in the through-holes is developed away to expose the conductive layer. The through-holes are filled with a conductive material by electroplating the conductive layer. The photoresist is stripped in an ultrasonic bath wherein the photoresist separates from the through-hole wafer and wherein the filled through-holes separate from the polymer at an interface between the polymer and the conductive layer to complete separation of the through-hole via wafer from the sacrificial wafer.Type: ApplicationFiled: August 25, 2004Publication date: March 2, 2006Inventors: Chirayarikathuveedu Sankarapillai, Ranganathan Nagarajan, Mohanraj Soundarapandian
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Patent number: 6846725Abstract: A method for forming wafers having through-wafer vias for wafer-level packaging of devices, the method comprising the steps of depositing metal on one of two wafers; bonding the two wafers using the metal deposited on the one of the two wafers; forming a through-wafer via in one of the two wafers; filling the through-wafer via with a conductive material; and forming a cavity in the one of the two wafers having the through-wafer via wherein the cavity is superposable over a device.Type: GrantFiled: January 27, 2003Date of Patent: January 25, 2005Assignee: Institute of MicroelectronicsInventors: Ranganathan Nagarajan, Chirayarikathuveedu Sankarapillai Premachandran, Yu Chen, Vaidyanathan Kripesh