Patents by Inventor Chirn Chye Boon
Chirn Chye Boon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11411000Abstract: A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed.Type: GrantFiled: January 4, 2021Date of Patent: August 9, 2022Assignees: MASSACHUSETTS INSTITUTE OF TECHNOLOGY, NANYANG TECHNOLOGICAL UNIVERSITYInventors: Pilsoon Choi, Chirn-Chye Boon, Li-Shiuan Peh
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Patent number: 11303316Abstract: An apparatus and method for wireless communication, and a method of fabricating the apparatus. The apparatus comprises two or more transceiver array groups, each transceiver array group comprising one or more radio frequency, RF, circuits, and one or more RF front end, RF FE, circuits; wherein the transceiver array groups are configured to operate at different frequencies; wherein the transceiver array groups are configured to be connected to one corresponding digital baseband processor; and wherein the transceiver array groups comprise at least one first transceiver array group configured to operate at cm wavelength or larger. Preferably, the transceiver array groups comprise at least one second transceiver array group configured to operate at mm wavelength.Type: GrantFiled: May 10, 2019Date of Patent: April 12, 2022Assignees: Nanyang Technological University, Massachusetts Institute of TechnologyInventors: Pilsoon Choi, Dimitri Antoniadis, Chirn Chye Boon, Eugene A. Fitzgerald
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Signal receiving circuit, signal processing chip, communications device, and signal receiving method
Patent number: 11128333Abstract: A signal receiving circuit amplifies a radio frequency signal by using a first radio frequency amplifier, outputs a first amplified signal in a same phase, amplifies the radio frequency signal by using a second radio frequency amplifier, and outputs a second amplified signal at an inverse phase. A first mixer mixes a first local oscillator signal with the first amplified signal to obtain a first frequency mixing signal, and a second mixer mixes a second local oscillator signal with the second amplified signal to obtain a second frequency mixing signal, where a phase of the first local oscillator signal is opposite to a phase of the second local oscillator signal. After adding the first frequency mixing signal and the second frequency mixing signal, an output interface outputs the first frequency mixing signal and the second frequency mixing signal.Type: GrantFiled: June 25, 2020Date of Patent: September 21, 2021Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Kaituo Yang, Xiang Yi, Chirn Chye Boon, Junping Zhang -
Publication number: 20210250057Abstract: An apparatus and method for wireless communication, and a method of fabricating the apparatus. The apparatus comprises two or more transceiver array groups, each transceiver array group comprising one or more radio frequency, RF, circuits, and one or more RF front end, RF FE, circuits; wherein the transceiver array groups are configured to operate at different frequencies; wherein the transceiver array groups are configured to be connected to one corresponding digital baseband processor; and wherein the transceiver array groups comprise at least one first transceiver array group configured to operate at cm wavelength or larger. Preferably, the transceiver array groups comprise at least one second transceiver array group configured to operate at mm wavelength.Type: ApplicationFiled: May 10, 2019Publication date: August 12, 2021Applicants: Nanyang Technological University, Massachusetts Institute of TechnologyInventors: Pilsoon Choi, Dimitri Antoniadis, Chirn Chye Boon, Eugene Fitzgerald
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Publication number: 20210151436Abstract: A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed.Type: ApplicationFiled: January 4, 2021Publication date: May 20, 2021Applicants: Massachusetts Institute of Technology, Nanyang Technological UniversityInventors: Pilsoon CHOI, Chirn-Chye BOON, Li-Shiuan PEH
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Patent number: 10923473Abstract: A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed.Type: GrantFiled: February 16, 2017Date of Patent: February 16, 2021Assignees: MASSACHUSETTS INSTITUTE OF TECHNOLOGY, NANYANG TECHNOLOGICAL UNIVERSITYInventors: Pilsoon Choi, Chirn-Chye Boon, Li-Shiuan Peh
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SIGNAL RECEIVING CIRCUIT, SIGNAL PROCESSING CHIP, COMMUNICATIONS DEVICE, AND SIGNAL RECEIVING METHOD
Publication number: 20200328769Abstract: A signal receiving circuit amplifies a radio frequency signal by using a first radio frequency amplifier, and outputs a first amplified signal in a same phase; amplifies the radio frequency signal by using a second radio frequency amplifier, and outputs a second amplified signal at an inverse phase. A first mixer mixes a first local oscillator signal with the first amplified signal to obtain a first frequency mixing signal; a second mixer mix a second local oscillator signal with the second amplified signal to obtain a second frequency mixing signal, where a phase of the first local oscillator signal is opposite to a phase of the second local oscillator signal; and after adding the first frequency mixing signal and the second frequency mixing signal, an output interface outputs the first frequency mixing signal and the second frequency mixing signal.Type: ApplicationFiled: June 25, 2020Publication date: October 15, 2020Inventors: Kaituo YANG, Xiang YI, Chirn Chye BOON, Junping ZHANG -
Patent number: 10707750Abstract: A charge-based charge pump with wide output voltage range is provided. In the charge-based charge pump, the digital logic circuit is configured to receive an up pulse signal and a down pulse signal and output a plurality of switching signals for controlling the first NMOS, the positive hold subcircuit, the first dynamic body-bias generator, the positive charge transfer subcircuit, the first static body-bias generator, the first PMOS, the negative hold subcircuit, the second dynamic body-bias generator, the negative charge transfer subcircuit and the second static body-bias generator electrically connected therewith, so as to allow the output voltage to range from ?0.84·VDD to 1.82·VDD. The charge-based charge pump is triggered by the up or down pulse signal or works in a default state, and the top plate and the bottom plate of the pump capacitor are electrically connected to different node and terminal according to the plurality of switching signals.Type: GrantFiled: July 5, 2019Date of Patent: July 7, 2020Assignee: DELTA ELECTRONICS INT'L (SINGAPORE) PTE LTDInventors: Devrishi Khanna, Chirn Chye Boon, Kaituo Yang, Jack Sheng Kee
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Publication number: 20200168605Abstract: A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed.Type: ApplicationFiled: February 16, 2017Publication date: May 28, 2020Applicants: Massachusetts Institute of Technology, Nanyang Technological UniversityInventors: Pilsoon CHOI, Chirn-Chye BOON, Li-Shiuan PEH
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Patent number: 10659011Abstract: A low noise amplifier is provided. The low noise amplifier includes an input port, an output port, an inverter, a plurality of switched-capacitor units and a feedback inductor. The inverter is electrically connected between the input port and the output port. Each of the plural switched-capacitor units is electrically connected with the inverter in parallel and includes a switch and a capacitor connected in series. The feedback inductor is electrically connected with the inverter in parallel.Type: GrantFiled: October 22, 2018Date of Patent: May 19, 2020Assignee: DELTA ELECTRONICS INT'L (SINGAPORE) PTE LTDInventors: Kaituo Yang, Chirn Chye Boon, Devrishi Khanna, Jack Sheng Kee
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Publication number: 20200127644Abstract: A low noise amplifier is provided. The low noise amplifier includes an input port, an output port, an inverter, a plurality of switched-capacitor units and a feedback inductor. The inverter is electrically connected between the input port and the output port. Each of the plural switched-capacitor units is electrically connected with the inverter in parallel and includes a switch and a capacitor connected in series. The feedback inductor is electrically connected with the inverter in parallel.Type: ApplicationFiled: October 22, 2018Publication date: April 23, 2020Inventors: Kaituo Yang, Chirn Chye Boon, Devrishi Khanna, Jack Sheng Kee
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Patent number: 10394191Abstract: A time-to-digital converter is provided. The time-to-digital converter comprises an oscillator controller, an invertible oscillator and a measurement circuit. The oscillator controller receives a start signal and a stop signal and outputs a mode signal. The invertible oscillator is electrically connected with the oscillator controller for receiving the mode signal. The oscillation direction of the invertible oscillator is inverted according to the mode signal, and the invertible oscillator outputs plural delay signals. The measurement circuit is electrically connected with the invertible oscillator for receiving the plural delay signals. The measurement circuit receives a sampling signal, samples the plural delay signals in accordance with the sampling signal, and outputs an output signal.Type: GrantFiled: May 25, 2018Date of Patent: August 27, 2019Assignees: DELTA ELECTRONICS INT'L (SINGAPORE) PTE LTD, NANYANG TECHNOLOGICAL UNIVERSITYInventors: Zhipeng Liang, Chirn Chye Boon, Xiang Yi, Jack Sheng Kee
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Patent number: 10326480Abstract: The communication receiver comprises a mixer being configured to mix the communication signal with a periodic mixing signal having a mixing frequency fC to obtain a mixed communication signal, wherein the mixed communication signal comprises a first frequency spectrum portion comprising the spectral region of interest being situated around a frequency fRF+fC and a second frequency spectrum portion comprising the spectral range of interest being situated around fRF?fC; a first demodulator being configured to demodulate a first frequency channel of the plurality of frequency channels within the spectral range of interest of the first frequency spectrum portion on the basis of a first local oscillator frequency fLO1; and a second demodulator being configured to demodulate a second frequency channel of the plurality of frequency channels within the spectral region of interest of the second frequency spectrum portion on the basis of a second local oscillator frequency fLO2.Type: GrantFiled: November 3, 2017Date of Patent: June 18, 2019Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Dror Regev, Shimon Shilo, Doron Ezri, Chirn Chye Boon, Xiang Yi, Junping Zhang, Gengen Hu, Dong Liang, Sheng Liu
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Publication number: 20190020272Abstract: Integrated circuits, wafer level integrated III-V power device and CMOS driver device packages, and methods for fabricating products with integrated III-V power devices and silicon-based driver devices are provided. In an embodiment, a boost converter circuit includes an inductor; a power switch having a conducting state and blocking state; and a control circuit for controlling the power switch from the conducting state to the blocking state for controlling flow of the current in the inductor, wherein the control circuit comprises a silicon integrated circuit comprising bipolar CMOS transistors, wherein when the power switch comprises a first GaN transistor, and wherein the power switch and silicon integrated circuit are electrically and mechanically coupled by way of flip chip bonding.Type: ApplicationFiled: July 12, 2017Publication date: January 17, 2019Inventors: Donald DISNEY, Fanyi MENG, Xiang YI, Chirn Chye BOON
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Patent number: 9742424Abstract: An analog-to-digital converter (ADC) is provided, having two comparators, two digital-to-analog converters (DACs), and an adder circuit. The ADC receives an input value and, over a plurality of conversion cycles of the ADC, generates an output value representative of the input value. Each respective DAC generates a plurality of threshold levels, which are defined, at least in part, by predetermined redundancy levels that are binary-scaled. The comparator arrangement provides an output code in a respective conversion cycle and, for at least two adjacent conversion cycles, the two comparators collectively provide 2-bit output codes. The adder circuit provides a plurality of output bits of the output value, and is capable of overlapping and adding a first significant bit of the 2-bit output code provided for a predetermined conversion cycle with a second significant bit of the 2-bit output code provided for a previous conversion cycle to generate one output bit.Type: GrantFiled: January 6, 2017Date of Patent: August 22, 2017Assignee: Nanyang Technological UniversityInventors: Sunny Sharma, Chirn Chye Boon
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Publication number: 20170201268Abstract: An analog-to-digital converter (ADC) is provided, having two comparators, two digital-to-analog converters (DACs), and an adder circuit. The ADC receives an input value and, over a plurality of conversion cycles of the ADC, generates an output value representative of the input value. Each respective DAC generates a plurality of threshold levels, which are defined, at least in part, by predetermined redundancy levels that are binary-scaled. The comparator arrangement provides an output code in a respective conversion cycle and, for at least two adjacent conversion cycles, the two comparators collectively provide 2-bit output codes. The adder circuit provides a plurality of output bits of the output value, and is capable of overlapping and adding a first significant bit of the 2-bit output code provided for a predetermined conversion cycle with a second significant bit of the 2-bit output code provided for a previous conversion cycle to generate one output bit.Type: ApplicationFiled: January 6, 2017Publication date: July 13, 2017Inventors: Sunny Sharma, Chirn Chye Boon
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Patent number: 9603190Abstract: An integrated circuit (400) adapted for mobile communication is disclosed. The circuit comprises a first device layer formed of a first semiconductor material and having at least a first circuit portion (402); and a second device layer formed of a second semiconductor material different to the first semiconductor material and having at least a second circuit portion (404), wherein the first and second device layers are integrally formed, and the first circuit portion is electrically coupled to the second circuit portion to enable the mobile communication using first and second wireless communication protocols. A related mobile computing device is also disclosed.Type: GrantFiled: January 23, 2015Date of Patent: March 21, 2017Assignees: MASSACHUSETTS INSTITUTE OF TECHNOLOGY, NANYANG TECHNOLOGICAL UNIVERSITYInventors: Pilsoon Choi, Jason Gao, Nadesh Ramanathan, Chirn-Chye Boon, Suhaib Fahmy, Li-Shiuan Peh
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Publication number: 20160330795Abstract: An integrated circuit (400) adapted for mobile communication is disclosed. The circuit comprises a first device layer formed of a first semiconductor material and having at least a first circuit portion (402); and a second device layer formed of a second semiconductor material different to the first semiconductor material and having at least a second circuit portion (404), wherein the first and second device layers are integrally formed, and the first circuit portion is electrically coupled to the second circuit portion to enable the mobile communication using first and second wireless communication protocols. A related mobile computing device is also disclosed.Type: ApplicationFiled: January 23, 2015Publication date: November 10, 2016Applicants: MASSACHUSETTS INSTITUTE OF TECHNOLOGY, NANYANG TECHNOLOGICAL UNIVERSITYInventors: PILSOON CHOI, JASON GAO, NADESH RAMANATHAN, CHIRN-CHYE BOON, SUHAIB FAHMY, LI-SHIUAN PEH
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Patent number: 8237531Abstract: An inductor circuit with high quality (Q) factor includes a primary inductor and a compensation sub-circuit. The compensation sub-circuit is electrically isolated from the primary inductor. The compensation sub-circuit is magnetically coupled with the primary inductor to compensate the loss in the primary inductor.Type: GrantFiled: December 31, 2007Date of Patent: August 7, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Ping Qiu, Chirn Chye Boon, Johnny Kok Wai Chew, Kiat Seng Yeo, Manh Anh Do, Lap Chan, Suh Fei Lim
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Publication number: 20090167466Abstract: An inductor circuit with high quality (Q) factor includes a primary inductor and a compensation sub-circuit. The compensation sub-circuit is electrically isolated from the primary inductor. The compensation sub-circuit is magnetically coupled with the primary inductor to compensate the loss in the primary inductor.Type: ApplicationFiled: December 31, 2007Publication date: July 2, 2009Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD., NANYANG TECHNOLOGICAL UNIVERSITYInventors: Ping QIU, Chirn Chye BOON, Johnny Kok Wai CHEW, Kiat Seng YEO, Manh Anh DO, Lap CHAN, Suh Fei LIM