Abstract: The present invention provides a semiconductor memory device having a block write function to perform an image processing at a high speed for any region on an image plane. The semiconductor memory device comprises a column decoder circuit 1; a column address latch circuit 2; a write control circuit 3 including NMOS transistors 13; a column mask register 4 including registers 10; a color register 5 including registers 11n; a Y switch 6 including switches 14; a memory cell 7; a block write control circuit 8; a column mask control circuit 9 including NOR gates 12; a column address pre-decode circuit 15 corresponding to subordinate column addresses Y0, Y1 and Y2; and a column address pre-decode circuit 16 corresponding to superordinate column addresses Y3, Y4 and Y5.

Abstract: A redundancy check circuit is composed of the fuses corresponding to more significant column addresses and the fuses corresponding, for the ordinary write operation, to lesser significant column and also corresponding, for the block write operation, to the column mask signal. Thereby, during the block write operation, the lesser significant column addresses are invalidated and the redundancy signal can be outputted depending on the redundancy check result and the column mask check result of more significant addresses.