Abstract: A timing controller that controls a drive circuit of a display panel includes: a delay output unit configured to output a delay value based on a delay time of a second pulse with respect to a first pulse that is output by the drive circuit, the first pulse being generated in synchronization with a data signal supplied to the display panel; and an error output unit configured to compare the delay value and a threshold value to each other and output an error signal based on a result of the comparison, and the second pulse is a pulse that is output from the drive circuit based on the first pulse.

Abstract: A circuit device in which a processing load of a processing device with respect to error detection performed on image data can be reduced, and an electro-optical device, an electronic apparatus, a mobile body, an error detection method and the like. The circuit device includes: an interface unit that receives image data; and an error detection unit that performs error detection. The interface unit receives the image data including display image data and error detection data that includes at least position information regarding an error detection region, and the error detection unit performs the error detection on the display image data based on the display image data of the error detection region that is specified by the position information.

Abstract: A timing controller that controls a drive circuit of a display panel includes: a delay output unit configured to output a delay value based on a delay time of a second pulse with respect to a first pulse that is output by the drive circuit, the first pulse being generated in synchronization with a data signal supplied to the display panel; and an error output unit configured to compare the delay value and a threshold value to each other and output an error signal based on a result of the comparison, and the second pulse is a pulse that is output from the drive circuit based on the first pulse.

Abstract: A circuit device in which a processing load of a processing device with respect to error detection performed on image data can be reduced, and an electro-optical device, an electronic apparatus, a mobile body, an error detection method and the like. The circuit device includes: an interface unit that receives image data; and an error detection unit that performs error detection. The interface unit receives the image data including display image data and error detection data that includes at least position information regarding an error detection region, and the error detection unit performs the error detection on the display image data based on the display image data of the error detection region that is specified by the position information.

Abstract: A display control device includes a first interface unit that receives display information of a first display method that includes image data and a control information setting unit that sets control information used for controlling display of an image in the display unit in accordance with setting information that specifies a display method. The display control device further includes an image data conversion unit that converts, if a second display method is specified by the setting information, the image data of the first display method type to image data of the second display method type in accordance with the control information. The display control device also includes a second interface unit that outputs the image data of the first or the second display method type in accordance with the setting information, and outputs signals for controlling the display unit in accordance with the control information.

Abstract: A display control device includes a first interface unit that receives display information of a first display method that includes image data and a control information setting unit that sets control information used for controlling display of an image in the display unit in accordance with setting information that specifies a display method. The display control device further includes an image data conversion unit that converts, if a second display method is specified by the setting information, the image data of the first display method type to image data of the second display method type in accordance with the control information. The display control device also includes a second interface unit that outputs the image data of the first or the second display method type in accordance with the setting information, and outputs signals for controlling the display unit in accordance with the control information.

Abstract: A first image data interface section is disposed in an electrode region and an input/output buffer region provided along a first side of a semiconductor chip. A second image data interface section is disposed in an electrode region and an input/output buffer region provided along a second side. A first memory interface section is disposed in an electrode region and an input/output buffer region provided along a third side. A second memory interface section is disposed in an electrode region and an input/output buffer region provided along a fourth side.

Abstract: The interlace/progressive conversion section of an image processing device sequentially receives image data corresponding to odd-numbered lines or sequentially receives image data corresponding to even-numbered lines. The interlace/progressive conversion section performs an even-numbered-line interpolation process that uses sequentially-received image data corresponding to first and second odd-numbered lines and generates image data corresponding to an even-numbered line between the first and second odd-numbered lines, or an odd-numbered-line interpolation process that uses sequentially-received image data corresponding to first and second even-numbered lines and generates image data corresponding to an odd-numbered line between the first and second even-numbered lines.

Abstract: A first image data interface section is disposed in an electrode region and an input/output buffer region provided along a first side of a semiconductor chip. A second image data interface section is disposed in an electrode region and an input/output buffer region provided along a second side. A first memory interface section is disposed in an electrode region and an input/output buffer region provided along a third side. A second memory interface section is disposed in an electrode region and an input/output buffer region provided along a fourth side.

Abstract: A TCP/IP (Transmission Control Protocol/Internet Protocol) reception processing circuit for transferring a packet included in a frame and received from a lower layer to a memory accessible by an upper layer, includes a section that presumes a communication end point as a destination of the packet included in the frame and received from the lower layer and starts transfer of the packet to the communication end point presumed as the destination of the packet in parallel with specifying the communication end point as the destination of the packet, and a section that stops the transfer of the packet to the communication end point presumed as the destination of the packet and starting transfer of the packet to the communication end point specified as the destination of the packet in response to the communication end point specified as the destination of the packet if the communication end point presumed as the destination of the packet is unmatched with the communication end point specified as the destination of t

Abstract: A transmission control protocol/Internet protocol (TCP/IP) reception processing circuit that transmits a packet included in a frame and received from a lower layer to memory accessible by an upper layer, in that: the memory includes: a communication endpoint information area which contains a plurality of packet storage areas, with each packet storage area storing a plurality of packets addressed to a predetermined communication endpoint, and which contains a plurality of descriptor tables linked to a first pointer included in each packet storage area, with each descriptor table having a second pointer that points out the packet storage area and having packet writable/non-writable information that indicates whether or not the packet can be written into the packet storage area pointed out by the second pointer; and, if a packet included in a frame and received from the lower layer is a packet addressed to the predetermined communication endpoint, one out of the plurality of descriptor tables that points out the