Abstract: An apparatus including a first register, a second register, and a control logic. The first register may be configured to store requests from a plurality of clients for a current cycle. The second register may be configured to store an indicator value indicating which of the plurality of clients received a grant in a previous cycle. The control logic may be configured to determine which of the plurality of clients having a request in the current cycle receives a grant based upon (i) a pointer value and (ii) the indicator value.

Abstract: An apparatus including a first register, a second register, and a control logic. The first register may be configured to store requests from a plurality of clients for a current cycle. The second register may be configured to store an indicator value indicating which of the plurality of clients received a grant in a previous cycle. The control logic may be configured to determine which of the plurality of clients having a request in the current cycle receives a grant based upon (i) a pointer value and (ii) the indicator value.

Abstract: A method provides for verifying soft error handling in an integrated circuit (IC) design. A diagnostic program is executed on a virtual IC based on the IC design using a simulator. A soft error is injected into the virtual IC to trigger hardware error correction in the virtual IC and a software exception. A record of a type and a location of the soft error at the time of the injecting is created. The error log generated by hardware error correction is then compared with the record of injected error, the hardware error correction being part of the virtual IC. An IC design flaw is indicated when a discrepancy exists between the error log and the record of the injected error.