Abstract: A frame rate conversion apparatus for 3D display is provided. The frame rate conversion apparatus for 3D display is capable of preserving alternate display of left and right frames while also preventing an issue of frame tearing. The frame rate conversion apparatus includes a storage unit, an input controller and an output controller. The input controller inputs an input frame sequence to the storage unit according to an input frame rate. The input frame sequence includes a plurality of frame pairs each having a left frame and a corresponding right frame. The output controller alternately outputs one of the left frames and one of the right frames from the storage unit according to an output frame rate and left/right frame information associated with the frame pairs in the storage unit to form an output frame sequence.

Abstract: An auto phase detection apparatus for automatically detecting a target sampling phase is provided. The auto phase detection apparatus includes a phase decider for generating a plurality of phase control signals; a sample clock generator, coupled to the phase decider, for generating a plurality of sample clock signals according to the phase control signals; an analog-to-digital converter (ADC), coupled to the sample clock generator, for converting an analog video signal to a digital signal according to the sample clock signals; a phase detector, coupled to the ADC and the phase decider, for generating a plurality of phase detection results according to the digital signal; and a motion detector, coupled to the ADC and the phase decider, for generating a motion detection result by detecting a motion in the digital signal. The phase decider determines the target sampling phase from the phase control signals according to the phase detection results and the motion detection result.

Abstract: A frame rate conversion apparatus for 3D display is provided. The frame rate conversion apparatus for 3D display is capable of preserving alternate display of left and right frames while also preventing an issue of frame tearing. The frame rate conversion apparatus includes a storage unit, an input controller and an output controller. The input controller inputs an input frame sequence to the storage unit according to an input frame rate. The input frame sequence includes a plurality of frame pairs each having a left frame and a corresponding right frame. The output controller alternately outputs one of the left frames and one of the right frames from the storage unit according to an output frame rate and left/right frame information associated with the frame pairs in the storage unit to form an output frame sequence.

Abstract: An auto phase detection apparatus for automatically detecting a target sampling phase is provided. The auto phase detection apparatus includes a phase decider for generating a plurality of phase control signals; a sample clock generator, coupled to the phase decider, for generating a plurality of sample clock signals according to the phase control signals; an analog-to-digital converter (ADC), coupled to the sample clock generator, for converting an analog video signal to a digital signal according to the sample clock signals; a phase detector, coupled to the ADC and the phase decider, for generating a plurality of phase detection results according to the digital signal; and a motion detector, coupled to the ADC and the phase decider, for generating a motion detection result by detecting a motion in the digital signal. The phase decider determines the target sampling phase from the phase control signals according to the phase detection results and the motion detection result.

Abstract: A vertex shader. The vertex shader comprises an instruction register file, a flow controller, a thread arbitrator, and an arithmetic logic unit (ALU) pipe. The instruction register file stores a plurality of instructions. The flow controller concurrently executing a plurality of threads, reads the instructions in order from the instruction register file for the threads and accesses vertex data for the threads. The thread arbitrator checks the dependency of instructions in the threads and selects the thread to execute in accordance with the result of the dependency check and a thread execution priority. The arithmetic logic unit (ALU) pipe receives the vertex data for executing the instructions of the thread selected by the thread arbitrator for three-dimensional (3D) graphics computations.

Abstract: A logic unit is provided for performing operations in multiple threads on vertex data. The logic unit comprises a macro instruction register file, a flow control instruction register file, and a flow controller. The macro instruction register file stores macro blocks with each macro block including at least one instruction. The flow control instruction register file stores flow control instructions with each flow control instruction including at least one called macro block and dependency information of the called macro block.