Abstract: Described are MEMS mirror arrays monolithically integrated with CMOS control electronics. The MEMS arrays include polysilicon or polysilicon-germanium components that are mechanically superior to metals used in other MEMS applications, but that require process temperatures not compatible with conventional CMOS technologies. CMOS circuits used with the polysilicon or polysilicon-germanium MEMS structures use interconnect materials that can withstand the high temperatures used during MEMS fabrication. These interconnect materials include doped polysilicon, polycides, and tungsten metal.

Abstract: Described are MEMS mirror arrays monolithically integrated with CMOS control electronics. The MEMS arrays include polysilicon or polysilicon-germanium components that are mechanically superior to metals used in other MEMS applications, but that require process temperatures not compatible with conventional CMOS technologies. CMOS circuits used with the polysilicon or polysilicon-germanium MEMS structures use interconnect materials that can withstand the high temperatures used during MEMS fabrication. These interconnect materials include doped polysilicon, polycides, and tungsten metal.

Abstract: A semiconductor dynamic memory device contains differential sense amplifiers for detecting the charge on bit lines, and active pull-up circuits for restoring bit lines to a full 1 level. The pull-up circuits are not activated on the dummy cell sides, however, because the power used to restore the dummy cell would be wasted since the dummy cell capacitors are always discharged. The device illustrated uses folded bit lines and multiplexed sense amplifiers; one of two opposite pairs of bit lines is selected. The two opposite pairs share precharge and active pull-up circuits on one side of the array, and share column output lines on the opposite side. The multiplex circuitry selects one side or the other for sensing, and also couples precharge and boost voltages or read/write data back and forth from one side of the sense amplifier to the other.

Abstract: A -CMOS clock generator circuit is controlled by two clocks, one always going high before the other when entering an active cycle, and always going low before the other in entering a precharge cycle; this one clock precharges a capacitor through a P-channel transistor, and holds a drive node discharged. Two sets of semi-connected N-channel output transistors are used, with the gates of the top two driven by the drive node, and the gates of the bottom two driven by a CMOS inverter which has the second clock as its input. The inverter output also drives the gate of a P-channel transistor between the capacitor and the drive node. Another P-channel transistor with the first clock on its gate couples the drive node to the intermediate node of the first output pair. The second clock transfers the charge from the capacitor to the drive node, which also causes the capacitor to boot the drive node above the supply. When the first clock goes low it discharges the booted node to the supply rather than to ground.

Abstract: A semiconductor dynamic memory device contains differential sense amplifiers for detecting the charge on bit line halves which are of the folded type. The sense amplifiers are multiplexed so that one of two opposite pairs of bit line halves are selected. The two opposite pairs share precharge and active pull-up circuits on one side of the array, and share column output lines on the opposite side. Thus, the multiplex circuitry operates not only for selecting one side or the other for sensing, but also for coupling precharge and boost voltages or read/write data back and forth from one side of the sense amplifier to the other. The active pull-up circuits are activated in both read and write portions of a read-modify-write cycle.

Abstract: A dynamic MOS read/write memory has a substrate bias generator circuit which includes, in this example, four separate pump circuits. A first of these operates only during power-up to quickly produce the desired back bias; this pump circuit uses a high frequency oscillator and a low impedence drive, and cuts off to save power as soon as the necessary bias is reached. A second generates a smaller sustaining current, using a lower frequency oscillator and higher impedance drive; this functions to compensate for leakage during idle periods. The third and fourth pump circuits are driven by RAS and CAS, so these occur only when needed, and at a rate dependent upon the actual operating condition of the memory.