Abstract: A method and apparatus for stopping the internal clock of a microprocessor synchronously with the execution of an instruction is provided. A stop instruction is placed in a sequence of instructions to be executed by the microprocessor. The execution of the stop execution may store a stop value into a stop register of the microprocessor. Clock stop logic detects when the stop value has been stored into the stop register. The clock stop logic instructs a clock generation component, of the microprocessor, to cease generation of an internal clock signal, thereby preventing the microprocessor from changing state. As further instructions are not executed by the microprocessor, the state of the microprocessor reflects the execution of the instruction immediately prior to the stop instruction. The processing state of the microprocessor may be obtained for use in debugging the design of the microprocessor or the instructions executed thereby.

Abstract: The present invention solves the problems associated with the prior art by providing a latency prediction bit (LPB) to indicate the latency with which an instruction should be executed, implicitly indicating whether a data dependency is likely to exist and the likelihood of that dependency causing a hazard. In a processor according to the present invention, an instruction dependent upon a given LDI instruction is issued a given number of machine cycles after that LDI instruction, the number of machine cycles being based on the value of the LPB associated with that LDI instruction. The LPB's value, in turn, depends on whether data will need to be forwarded to the functional unit involved during the execution of LDI instruction. The ability to predict such hazards is important in maintaining a pipeline's throughput and avoiding unnecessary recirculations.