Patents by Inventor Chiu-Cheng Lin

Chiu-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12130551
    Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.
    Type: Grant
    Filed: June 15, 2023
    Date of Patent: October 29, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Hao Lee, You-Cheng Jhang, Han-Zong Pan, Jui-Chun Weng, Chiu-Hua Chung, Sheng-Yuan Lin, Hsin-Yu Chen
  • Patent number: 7615992
    Abstract: An apparatus for detecting an electronic device testing socket including a testing base, a detecting circuit board, a depth gauge, and a conductive pressing block is provided. The detecting circuit board disposed on the testing base has a carrying surface for carrying an electronic device testing socket. The electronic device testing socket includes a plurality of pin units, and each of the pin units includes an S-shaped pin and a pair of elastic rods accommodated within recesses thereof. The depth gauge disposed on the testing base presses against a top surface of the conductive pressing block, and presses with a bottom surface thereof against the electronic device testing socket. The depth gauge is adapted to adjust a distance between the top surface of the conductive pressing block and the carrying surface. The detecting circuit board is electrically connected to the pin units for detecting the status of the pin units.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: November 10, 2009
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ping-Cheng Wen, Wei-Jen Hsueh, Jen-Kuei Li, Chiu-Cheng Lin
  • Publication number: 20090189626
    Abstract: An apparatus for detecting an electronic device testing socket including a testing base, a detecting circuit board, a depth gauge, and a conductive pressing block is provided. The detecting circuit board disposed on the testing base has a carrying surface for carrying an electronic device testing socket. The electronic device testing socket includes a plurality of pin units, and each of the pin units includes an S-shaped pin and a pair of elastic rods accommodated within recesses thereof. The depth gauge disposed on the testing base presses against a top surface of the conductive pressing block, and presses with a bottom surface thereof against the electronic device testing socket. The depth gauge is adapted to adjust a distance between the top surface of the conductive pressing block and the carrying surface. The detecting circuit board is electrically connected to the pin units for detecting the status of the pin units.
    Type: Application
    Filed: March 26, 2008
    Publication date: July 30, 2009
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ping-Cheng Wen, Wei-Jen Hsueh, Jen-Kuei Li, Chiu-Cheng Lin
  • Patent number: 7109740
    Abstract: A method for re-testing semiconductor device includes following processes: (1) providing a first carrier for accommodating semiconductor devices which have been tested; (2) taking the semiconductor devices out from the first carrier and placing them according to the information of a fist map by a pick-and-place machine, wherein the information of the first map has the coordinates of the positions of the film frame where the semiconductor is to be placed; (3) placing the film frame with the semiconductor devices placed thereon to a testing machine, and re-testing the semiconductor devices according to the information of the first map by the tester; (4) placing the film frame with the semiconductor devices attached thereon to a pick-and-place machine, and taking the semiconductor devices out according to the result of the retesting from the film frame, and placing the semiconductor devices on at least one carriers.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: September 19, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chin-Chen Chuan, Chiu-Cheng Lin, Cheng Chieh Lee, Kuei Lin Huang, Yong Liang Chen, Jui Liang Wang, Pao Ta Chien, Hsiang-Han Kung, Chao Hsiung Hwu
  • Publication number: 20060022697
    Abstract: A method for re-testing semiconductor device includes following processes: (1) providing a first carrier for accommodating semiconductor devices which have been tested; (2) taking the semiconductor devices out from the first carrier and placing them according to the information of a fist map by a pick-and-place machine, wherein the information of the first map has the coordinates of the positions of the film frame where the semiconductor is to be placed; (3) placing the film frame with the semiconductor devices placed thereon to a testing machine, and re-testing the semiconductor devices according to the information of the first map by the tester; (4) placing the film frame with the semiconductor devices attached thereon to a pick-and-place machine, and taking the semiconductor devices out according to the result of the retesting from the film frame, and placing the semiconductor devices on at least one carriers.
    Type: Application
    Filed: June 28, 2005
    Publication date: February 2, 2006
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chin-Chen Chuan, Chiu-Cheng Lin, Cheng Lee, Kuei Huang, Yong Chen, Jui Wang, Pao Chien, Hsiang-Han Kung, Chao Hwu