Abstract: A pincer structure includes a first body having an immovable palate and an immovable stem, a second body having a movable palate and a movable stem, a clipping space defined by the movable palate and the immovable palate, the movable stem pivoted on the movable palate, an elastomer elastically connected between the movable palate and the immovable stem, a limiting member extruded from the movable stem, the limiting member having an abutting unit, a pivoting member pivoted on the movable stem, the pivoting member having an abutting portion, the abutting portion being movable between the movable stem and the abutting unit, a connecting member having one end and another end, said one end pivotally assembled to the pivoting member and said another end movably assembled to the immovable stem. Therefore, a recovery force of the elastomer makes the operation smooth.

Abstract: A nitrogen-free anti-reflective layer for use in semiconductor photolithography is fabricated in a chemical vapor deposition process, optionally plasma-enhanced, using a gaseous mixture of carbon, silicon, and oxygen sources. By varying the process parameters, a substantially hermetic layer with acceptable values of the refractive index n and extinction coefficient k can be obtained. The nitrogen-free moisture barrier anti-reflective layer produced by this technique improves plasma etch of features such as vias in subsequent processing steps.

Abstract: In certain embodiments, a method for tagging communications from a user system, such that a source of a malicious computer element in a computer network may be determined, includes determining tag information for a user system in the computer network, the tag information physically identifying the user system. The method further includes detecting an attempt to send a communication from the user system and, in response to detecting the attempt to send a communication from the user system, attaching the tag information to the communication prior to sending the communication from the user system. The attachment of the tag information to the communication allows the source of the communication to be determined in response to determining that the communication is associated with a malicious computer element, the source comprising the user system.

Abstract: A nitrogen-free anti-reflective layer for use in semiconductor photolithography is fabricated in a chemical vapor deposition process, optionally plasma-enhanced, using a gaseous mixture of carbon, silicon, and oxygen sources. By varying the process parameters, a substantially hermetic layer with acceptable values of the refractive index n and extinction coefficient k can be obtained. The nitrogen-free moisture barrier anti-reflective layer produced by this technique improves plasma etch of features such as vias in subsequent processing steps.

Abstract: In certain embodiments, a method for tagging communications from a user system, such that a source of a malicious computer element in a computer network may be determined, includes determining tag information for a user system in the computer network, the tag information physically identifying the user system. The method further includes detecting an attempt to send a communication from the user system and, in response to detecting the attempt to send a communication from the user system, attaching the tag information to the communication prior to sending the communication from the user system. The attachment of the tag information to the communication allows the source of the communication to be determined in response to determining that the communication is associated with a malicious computer element, the source comprising the user system.

Abstract: A method of forming a damascene structure above a substrate is provided. A low-k dielectric layer is formed over the substrate, wherein the low-k dielectric layer does not have a trench stop layer. A plurality of vias are etched through the low-k dielectric layer. Via plugs are formed in the plurality of vias. A plurality of trenches are etched into the low-k dielectric layer, wherein the etching with sufficiently high via plugs minimizes facet formation at the tops of vias exposed to the etch and wherein the trench etch process removes fences caused by the via plugs. The via plugs are stripped.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a TiAlON bottom electrode diffusion barrier layer prior to formation of the bottom electrode layer in an FeRAM capacitor stack. Subsequently, when performing the capacitor stack etch, the portion of the TiAlON diffusion barrier layer not covered by the FeRAM capacitor stack is etched substantially anisotropically due to the oxygen within the TiAlON diffusion barrier layer substantially preventing a lateral etching thereof. In the above manner, an undercut of the TiAlON diffusion barrier layer under the FeRAM capacitor stack is prevented. In another aspect of the invention, a method of forming an FeRAM capacitor comprises forming a multi-layer bottom electrode diffusion barrier layer. Such formation comprises forming a TiN layer over the interlayer dielectric layer and the conductive contact and forming a diffusion barrier layer thereover.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes evaluating the capacitor stack to determine the efficacy of the sidewall diffusion barrier layer deposition. When evaluating the capacitor stack after etching a masking layer portion of the hard mask, if “ears” are seen on top of the stack, the sidewall diffusion barrier layer is sufficiently thick to provide an adequate sidewall barrier. Evaluation may be performed using a standard or tilt scanning electron microscope, for example.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a sidewall diffusion barrier prior to etching the bottom electrode diffusion barrier layer. The sidewall diffusion barrier layer is then etched prior to the bottom electrode diffusion barrier layer. In patterning an AlOx sidewall diffusion barrier layer prior to etching the underlying bottom electrode diffusion barrier layer, the etch chemistry comprises BCl3+Ar. The BCl3 is effective in etching the AlOx with a good selectivity to the underlying nitride hard mask on top of the capacitor stack (e.g., TiAlN) and nitride bottom electrode diffusion barrier (e.g., TiAlON with small oxygen content) between the neighboring capacitor stacks. The Ar may be added to the etch chemistry because the resulting surface (of a top portion of the hard mask and the bottom electrode diffusion barrier) is smoother.

Abstract: Processes for etching PZT and/or forming a ferroelectric capacitor with Ir/IrOx electrodes and a PZT ferroelectric layer use a titanium-containing hard mask, a chlorine/oxygen-based plasma, and a hot substrate, typically at about 350 ° C. The processes add a fluorine-containing compound such as CHF3 to the chlorine/oxygen-based plasma for etching of the PZT layer and add nitrogen to improve sidewall profiles when etching Ir layers. The chlorine/oxygen-based plasmas provide good selectivity with high etch rates for Ir and PZT layers and low etch rates for the hard mask.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a sidewall diffusion barrier prior to etching the bottom electrode diffusion barrier layer. The sidewall diffusion barrier layer is then etched prior to the bottom electrode diffusion barrier layer. In patterning an AlOx sidewall diffusion barrier layer prior to etching the underlying bottom electrode diffusion barrier layer, the etch chemistry comprises BCl3+Ar. The BCl3 is effective in etching the AlOx with a good selectivity to the underlying nitride hard mask on top of the capacitor stack (e.g., TiAlN) and nitride bottom electrode diffusion barrier (e.g., TiAlON with small oxygen content) between the neighboring capacitor stacks. The Ar may be added to the etch chemistry because the resulting surface (of a top portion of the hard mask and the bottom electrode diffusion barrier) is smoother.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a TiAlON bottom electrode diffusion barrier layer prior to formation of the bottom electrode layer in an FeRAM capacitor stack. Subsequently, when performing the capacitor stack etch, the portion of the TiAlON diffusion barrier layer not covered by the FeRAM capacitor stack is etched substantially anisotropically due to the oxygen within the TiAlON diffusion barrier layer substantially preventing a lateral etching thereof. In the above manner, an undercut of the TiAlON diffusion barrier layer under the FeRAM capacitor stack is prevented. In another aspect of the invention, a method of forming an FeRAM capacitor comprises forming a multi-layer bottom electrode diffusion barrier layer. Such formation comprises forming a TiN layer over the interlayer dielectric layer and the conductive contact and forming a diffusion barrier layer thereover.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes evaluating the capacitor stack to determine the efficacy of the sidewall diffusion barrier layer deposition. When evaluating the capacitor stack after etching a masking layer portion of the hard mask, if “ears” are seen on top of the stack, the sidewall diffusion barrier layer is sufficiently thick to provide an adequate sidewall barrier. Evaluation may be performed using a standard or tilt scanning electron microscope, for example.

Abstract: The new heteropolysaccharide NW-01 prepared by the fermentation of a Flavobacterium species ATCC 53201 has valuable properties as a viscosity and mobility cotrol agent in aqueous systems and useful in preparing oil well drilling fluids. Its chemical composition consists of glucose, arabinose and galactose in a 4.8:3.3:1 molar ratio.