Patents by Inventor Chiu-Chun Wang

Chiu-Chun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240431066
    Abstract: Heat exchange apparatuses and methods for hyperbaric cooling fan applications such as computing devices. The apparatus comprises a material with high thermal conductivity and is configured to be overlaid on an internal surface of the housing, such that an internal surface of the apparatus is exposed to the hot air flowing inside the housing, and an external surface of the apparatus occludes at least some of the existing through-holes of the housing. In operation, the apparatus converts the through-holes into passive heat exchanging regions that passively transfer heat from inside the housing to outside the housing, which brings the internal air temperature and junction temperature (Tj) of the heat generating components down. Provided embodiments do not require reworking of the original industrial design (ID) of the housing.
    Type: Application
    Filed: June 23, 2023
    Publication date: December 26, 2024
    Applicant: Intel Corporation
    Inventors: Jeff Ku, Chi Chou Cheng, Jeffrey Ho, Chih-Tsung Hu, Srinivasarao Konakalla, Tsung-Kai Lin, Arnab Sen, Chiu-Chun Wang, Jiacheng Wu
  • Patent number: 8953111
    Abstract: A pixel array includes scan lines, data lines, sub-pixel units, capacitor electrode line sets, and connecting structure sets that are all disposed on a substrate. Each sub-pixel unit has at least one active device and at least one pixel electrode electrically connected to the active device, and the active device is electrically connected to one of the scan lines and one of the data lines. Each capacitor electrode line set has N capacitor electrode lines, the N capacitor electrode lines partially overlap with the pixel electrode of each of the sub-pixel units to form a plurality of storage capacitors, and N?2. The N capacitor electrode lines in each capacitor electrode line set are electrically connected to one another by each connecting structure set, and there is no connecting structure located between the capacitor electrode line sets having the connecting structures therein.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: February 10, 2015
    Assignee: Au Optronics Corporation
    Inventors: Chiu-Chun Wang, Tsung-Yuan Tsui, Chai-Ling Lai, Chi-Kao Tang
  • Publication number: 20110317085
    Abstract: A pixel array includes scan lines, data lines, sub-pixel units, capacitor electrode line sets, and connecting structure sets that are all disposed on a substrate. Each sub-pixel unit has at least one active device and at least one pixel electrode electrically connected to the active device, and the active device is electrically connected to one of the scan lines and one of the data lines. Each capacitor electrode line set has N capacitor electrode lines, the N capacitor electrode lines partially overlap with the pixel electrode of each of the sub-pixel units to form a plurality of storage capacitors, and N?2. The N capacitor electrode lines in each capacitor electrode line set are electrically connected to one another by each connecting structure set, and there is no connecting structure located between the capacitor electrode line sets having the connecting structures therein.
    Type: Application
    Filed: September 2, 2010
    Publication date: December 29, 2011
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Chiu-Chun Wang, Tsung-Yuan Tsui, Chai-Ling Lai, Chi-Kao Tang