Abstract: A damascene process for introducing copper into metallization layers in microelectronic structures includes a step of forming an enhancement layer of a metal alloy, such as a copper alloy or Co—W—P, over the barrier layer, using PVD, CVD or electrochemical deposition prior to electrochemically depositing copper metallization. The enhancement layer has a thickness from 10&mgr; to 100&mgr; and conformally covers the discontinuities, seams and grain boundary defects in the barrier layer. The enhancement layer provides a conductive surface onto which a metal layer, such as copper metallization, may be applied with electrochemical deposition. Alternatively, a seed layer may be deposited over the enhancement layer prior to copper metallization.

Abstract: A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias etches a via opening in a first insulating layer. A photoresist layer that the defines the conductive wiring is deposited and patterned on the first insulating layer after the via opening has been created. The via opening and the conductive wire opening in the resist layer are then filled with the conductive material, such as copper. The resist layer may then be removed and a second insulating layer provided over the first insulating layer.

Abstract: Methods for electrochemically polishing copper films on semiconductor substrates use an alkaline solution with a pH in the range of about 8.0 to 10.5. A constant current density of from 5 to 100 amperes per square foot is applied to an electrochemical cell formed by an electrode, the alkaline solution and the copper film. Copper is removed at a rate of from 500 to 10,000 angstroms per minute. The end point for the electro-polishing is detected by a sudden change in applied voltage. The alkaline polishing solution may also contain copper ions so that when the current direction is reversed, copper is deposited onto the copper film. Furthermore, this copper deposition will occur selectively on the exposed copper surface but not on the exposed barrier layer surface. Hence, the method can compensate for dishing and erosion by re-depositing copper in regions after too much copper was removed from those regions.

Abstract: A multiple station processing chamber used to deposit and/or remove a material on a semiconductor wafer is described. The multiple station processing chamber is comprised of two or more processing stations at which the wafer is exposed to a processing fluid. The processing stations are positioned within the chamber such that the wafer may be moved from station to station while remaining within the chamber. Each station of the multiple station processing chamber may have a fluid containment ring used for containment, disposal, and/or reuse of the electrolyte used to process the wafer at that particular processing station. The wafer is brought to the first processing station on a wafer support and exposed to a first processing fluid, which is then diverted into fluid containment ring for the first processing station. The wafer is then moved to a second processing chamber where the process is repeated with a second processing fluid.

Abstract: A multiple station processing chamber used to deposit and/or remove a material on a semiconductor wafer is described. The multiple station processing chamber is comprised of two or more processing stations at which the wafer is exposed to a processing fluid. The processing stations are positioned within the chamber such that the wafer may be moved from station to station while remaining within the chamber. Each station of the multiple station processing chamber may have a fluid containment ring used for containment, disposal, and/or reuse of the electrolyte used to process the wafer at that particular processing station. The wafer is brought to the first processing station on a wafer support and exposed to a first processing fluid, which is then diverted into fluid containment ring for the first processing station. The wafer is then moved to a second processing chamber where the process is repeated with a second processing fluid.

Abstract: A fluid containment ring for use in a processing chamber used to deposit a material onto a semiconductor wafer and/or remove material from a wafer by subjecting the wafer to an electric field and an electrolyte is described. The fluid containment ring is located at the base of the processing chamber in close proximity to the outside edge of the wafer being processed in the processing chamber. After each processing step is completed, the used electrolyte is diverted from the processing chamber into the fluid containment ring for containment such that no electrolyte contacts the unprocessed side (or back) of the wafer. One or more drains coupled to the fluid containment ring provide means for disposal and/or recirculation of the electrolyte.

Abstract: A processing chamber for depositing and/or removing material onto/from a semiconductor wafer when the wafer is subjected to an electrolyte and in an electric field, and in which the electrolyte is introduced and/or evacuated from a closely confined containment region. A hollow sleeve is utilized to form a containment chamber for holding the electrolyte. A wafer residing on a support is moved vertically upward to engage the sleeve to form an enclosing floor for the containment chamber. One electrode is disposed within the containment chamber while the opposite electrode is comprised of several electrodes distributed around the circumference of the wafer. The electrodes are also protected from the electrolyte when the support is raised and engaged to the sleeve. In one embodiment, the support and the sleeve are stationary during processing, while in another embodiment, both are rotated or oscillated during processing.

Abstract: A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias etches a via opening in a first insulating layer. A photoresist layer that the defines the conductive wiring is deposited and patterned on the first insulating layer after the via opening has been created. The via opening and the conductive wire opening in the resist layer are then filled with the conductive material, such as copper. The resist layer may then be removed and a second insulating layer provided over the first insulating layer.

Abstract: A processing chamber for depositing and/or removing material onto/from a semiconductor wafer when the wafer is subjected to an electrolyte and in an electric field, and in which a rotating anode is used to agitate and distribute the electrolyte. A hollow sleeve is utilized to form a containment chamber for holding the electrolyte. A wafer residing on a support is moved vertically upward to engage the sleeve to form an enclosing floor for the containment chamber. One electrode is disposed within the containment chamber while the opposite electrode is comprised of several electrodes distributed around the circumference of the wafer. The electrodes are also protected from the electrolyte when the support is raised and engaged to the sleeve. In one embodiment, the support and the sleeve are stationary during processing, while a rotating anode is used to agitate and distribute the electrolyte.

Abstract: An apparatus and method for customizing electrode contact placement on a semiconductor wafer while depositing and/or removing a material on a semiconductor wafer. The present invention is a adapter having at least one opening through which at least one electrode contacts the semiconductor wafer. The adapter may be designed to have multiple openings at specified locations on the adapter, thus allowing multiple electrode contacts with the semiconductor wafer at pre-specified locations. A conductive sheet may couple with the adapter to carry an electrical current from an electrical conductor to the electrode contacts placed within the openings of the adapter.

Abstract: An apparatus and method for providing an integrated processing system allowing for the isolation of non-compatible processes used to deposit a material onto a semiconductor wafer and/or remove material from a wafer is described. The integrated processing system of the present invention is comprised of a first processing chamber for processing a substrate in a first environment coupled to a second processing chamber for processing a substrate in a second environment. A connecting interface coupled to the first and second processing chambers allows the first and second processing chambers to be isolated from each other as needed. Further, the connecting interface allows a wafer to be transferred from the first processing chamber to the second processing chamber within a controlled environment. The first and second processing chambers may be or may include cluster tools.

Abstract: A processing chamber for depositing and/or removing material onto/from a semiconductor wafer when the wafer is subjected to an electrolyte and in an electric field. A hollow sleeve is utilized to form a containment chamber for holding the electrolyte. A wafer residing on a support is moved vertically upward to engage the sleeve to form an enclosing floor for the containment chamber. One electrode is disposed within the containment chamber while the opposite electrode is comprised of several electrodes distributed around the circumference of the wafer. The electrodes are also protected from the electrolyte when the support is raised and engaged to the sleeve. In one embodiment, the support and the sleeve are stationary during processing, while in another embodiment, both are rotated or oscillated during processing.

Abstract: A copper replenishment system for replenishing copper which is depleted from a copper plating solution. The replenishment is achieved by the use of a compact filter cartridge, which is inserted into a recirculating loop for the solution. The filter cartridge contains a chemical, which when reacting with the solution replenishes the copper into the solution. The filter cartridge is a compact unit which can be easily handled and reduces the amount of contaminants that could be introduced by the presence of the replenishment chemical.

Abstract: A method of utilizing electroless copper deposition to form interconnects on a semiconductor wafer. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is blanket deposited. Then, a contact displacement technique is used to form a thin activation seed layer of copper on the barrier layer. An electroless deposition technique is then used to auto-catalytically deposit copper on the activated barrier layer. The electroless copper deposition continues until the via/trench is filled. Subsequently, the surface is polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer.

Abstract: Described is a structure and process for forming a hermetically sealed chip. This hermetically sealed chip will greatly simplify packaging requirements and eventually lead to the realization of a "packageless chip". The hermetic sealing is composed of two parts, an extremely thin passivation layer which is deposited over the entire chip top and side surfaces and a passivation layer which is deposited over the bonding pad surface. Preferably, SiN is deposited as a chip surface passivation layer and Ni is selectively deposited as a metal passivation layer. The extremely thin nitride layer will minimize the stress and the amount of hydrogen in the SiN film and minimize deleterious effects upon device performance caused by stress and hydrogen. The thickness of the metal passivation layer may be the same as that of the dielectric layer so as to give a planar surface or it may be thick enough so as to give a protruding metal passivation bump.

Abstract: An electroless deposition apparatus and a method of electroless deposition that uses a single process chamber for performing multiple processes by moving through the process chamber a variety of fluids one at a time in a sequential order.

Abstract: A method for utilizing electroless copper deposition to form interconnects on a semiconductor. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is deposited. Then, a catalytic copper seed layer is conformally blanket deposited in vacuum over the barrier layer. Next, without breaking the vacuum, an aluminum protective layer is deposited onto the catalytic layer to encapsulate and protect the catalytic layer from oxidizing. An electroless deposition technique is then used to auto-catalytically deposit copper on the catalytic layer. The electroless deposition solution dissolves the overlying protective layer to expose the surface of the underlying catalytic layer. The electroless copper deposition occurs on this catalytic surface, and continues until the via/trench is filled.

Abstract: Described is a structure and process for forming a hermetically sealed chip. This hermetically sealed chip will greatly simplify packaging requirements and eventually lead to the realization of a "packageless chip". The hermetic sealing is composed of two parts, an extremely thin passivation layer which is deposited over the entire chip top and side surfaces and a passivation layer which is deposited over the bonding pad surface. Preferably, SiN is deposited as a chip surface passivation layer and Ni is selectively deposited as a metal passivation layer. The extremely thin nitride layer will minimize the stress and the amount of hydrogen in the SiN film and minimize deleterious effects upon device performance caused by stress and hydrogen. The thickness of the metal passivation layer may be the same as that of the dielectric layer so as to give a planar surface or it may be thick enough so as to give a protruding metal passivation bump.

Abstract: A technique for electrolessly depositing a CoWP barrier material on to copper and electrolessly depositing copper onto a CoWP barrier material to prevent copper diffusion when forming layers and/or structures on a semiconductor wafer.

Abstract: A method or utilizing electroless copper deposition to selectively form encapsulated copper plugs to connect conductive regions on a semiconductor. A via opening in an inter-level dielectric (ILD) provides a path for connecting two conductive regions separated by the ILD. Once the underlying metal layer is exposed by the via opening, a SiN or SiON dielectric encapsulation layer is formed along the sidewalls of the via. Then, a contact displacement technique is used to form a thin activation layer of copper on a barrier metal, such as TiN, which is present as a covering layer on the underlying metal layer. After the contact displacement of copper on the barrier layer at the bottom of the via, an electroless copper deposition technique is then used to auto-catalytically deposit copper in the via. The electroless copper deposition continues until the via is almost filled, but leaving sufficient room at the top in order to form an upper encapsulation layer.