Patents by Inventor Chiu-Hsiang Chou

Chiu-Hsiang Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6617650
    Abstract: A diode device for an electrostaticdischarge (ESD) protection circuit includes a P-type substrate, a buried N+ heavily doped semiconductor layer implanted in the P-type substrate and bounded by a deep trench isolation, a P well disposed above the buried N+ heavily doped semiconductor layer in the P-type substrate and isolated from the P-type substrate by the deep trench isolation. A P+ doped region, which serves as an anode of the diode device, is located in the P well. A N+ doped region, which serves as a cathode of the diode device, is laterally disposed in the P well and spaced apart from the P+ doped region. The P+ doped region, the buried N+ heavily doped semiconductor layer, and the P-type substrate constitute an open base parasitic PNP bipolar transistor.
    Type: Grant
    Filed: December 25, 2002
    Date of Patent: September 9, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Shiao-Shien Chen, Tien-Hao Tang, Chiu-Hsiang Chou