Patents by Inventor Chiu-Hsien Yeh
Chiu-Hsien Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10290736Abstract: A semiconductor device and a method of forming the same are provided. A substrate is provided. A trench is formed in the substrate and a conductive material is formed filling the trench. A portion of the conductive material filling an upper portion of the trench is removed to expose an upper surface of the substrate and an upper corner and an upper sidewall of the trench. A doping process is performed to form a doped region in the substrate along the exposed upper surface of the substrate and the exposed upper corner and upper sidewall of the trench. The doped region has an upside-down L shape.Type: GrantFiled: January 17, 2018Date of Patent: May 14, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Kai-Ping Chen, Li-Wei Feng, Kuei-Hsuan Yu, Chiu-Hsien Yeh
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Patent number: 10157744Abstract: A method for forming patterns of semiconductor device is provided in the present invention, with steps of filling up first self-assembly material in first openings in a dielectric layer, phase-separating the first self-assembly material to form a first portion and a second portion surrounding the first portion, removing the first portion and performing a first etch process to form a first mask pattern in a mask layer, forming a second dielectric layer and repeating the above steps to form a second mask pattern in the mask layer, wherein the second mask pattern is aligned with the first mask pattern to form a common mask pattern.Type: GrantFiled: February 1, 2018Date of Patent: December 18, 2018Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Kai-Ping Chen, Kuei-Hsuan Yu, Chiu-Hsien Yeh, Li-Wei Feng
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Patent number: 10151048Abstract: A manufacturing method of an epitaxial contact structure in a semiconductor memory device includes the following steps. A recess is formed in a semiconductor substrate by an etching process. An etching defect is formed in the recess by the etching process. An oxidation process is performed after the etching process. An oxide layer is formed in the recess by the oxidation process, and the etching defect is encompassed by the oxide layer. A cleaning process is performed after the oxidation process. The oxide layer and the etching defect encompassed by the oxide layer are removed by the cleaning process. An epitaxial growth process is performed to form an epitaxial contact structure in the recess after the cleaning process.Type: GrantFiled: November 29, 2017Date of Patent: December 11, 2018Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Wan-Chi Wu, Hui-Ling Chuang, Chih-Chi Cheng, Chiu-Hsien Yeh, Chien-Cheng Tsai, Hung-Jung Yan
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Publication number: 20180226251Abstract: A method for forming patterns of semiconductor device is provided in the present invention, with steps of filling up first self-assembly material in first openings in a dielectric layer, phase-separating the first self-assembly material to form a first portion and a second portion surrounding the first portion, removing the first portion and performing a first etch process to form a first mask pattern in a mask layer, forming a second dielectric layer and repeating the above steps to form a second mask pattern in the mask layer, wherein the second mask pattern is aligned with the first mask pattern to form a common mask pattern.Type: ApplicationFiled: February 1, 2018Publication date: August 9, 2018Inventors: Kai-Ping Chen, Kuei-Hsuan Yu, Chiu-Hsien Yeh, Li-Wei Feng
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Patent number: 10043882Abstract: A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. A barrier layer is then formed on the first region of the substrate. A first work function layer is formed on the barrier layer. An upper half portion of the first work function layer is converted into a non-volatile material layer. The non-volatile material layer is removed and a lower half portion of the first work function layer is kept.Type: GrantFiled: January 8, 2018Date of Patent: August 7, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Wen Su, Zhen Wu, Hsiao-Pang Chou, Chiu-Hsien Yeh, Shui-Yen Lu, Jian-Wei Chen
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Publication number: 20180212055Abstract: A semiconductor device and a method of forming the same are provided. A substrate is provided. A trench is formed in the substrate and a conductive material is formed filling the trench. A portion of the conductive material filling an upper portion of the trench is removed to expose an upper surface of the substrate and an upper corner and an upper sidewall of the trench. A doping process is performed to form a doped region in the substrate along the exposed upper surface of the substrate and the exposed upper corner and upper sidewall of the trench. The doped region has an upside-down L shape.Type: ApplicationFiled: January 17, 2018Publication date: July 26, 2018Inventors: Kai-Ping Chen, Li-Wei Feng, Kuei-Hsuan Yu, Chiu-Hsien Yeh
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Patent number: 10026827Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first organic layer on the substrate; patterning the first organic layer to form an opening; forming a second organic layer in the opening; and removing the first organic layer to form a patterned second organic layer on the substrate.Type: GrantFiled: April 10, 2016Date of Patent: July 17, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhen Wu, Chiu-Hsien Yeh, Po-Wen Su, Kuan-Ying Lai
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Publication number: 20180151685Abstract: A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. A barrier layer is then formed on the first region of the substrate. A first work function layer is formed on the barrier layer. An upper half portion of the first work function layer is converted into a non-volatile material layer. The non-volatile material layer is removed and a lower half portion of the first work function layer is kept.Type: ApplicationFiled: January 8, 2018Publication date: May 31, 2018Inventors: Po-Wen Su, Zhen Wu, Hsiao-Pang Chou, Chiu-Hsien Yeh, Shui-Yen Lu, Jian-Wei Chen
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Patent number: 9899491Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a conductive layer stacked one over another on the substrate. The second gate structure includes the barrier layer, a portion of the first work function layer and the conductive layer stacked one over another on the substrate, wherein the portion of the first work function layer has a smaller thickness than a thickness of the first work function layer.Type: GrantFiled: June 15, 2016Date of Patent: February 20, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Wen Su, Zhen Wu, Hsiao-Pang Chou, Chiu-Hsien Yeh, Shui-Yen Lu, Jian-Wei Chen
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Publication number: 20170330952Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a conductive layer stacked one over another on the substrate. The second gate structure includes the barrier layer, a portion of the first work function layer and the conductive layer stacked one over another on the substrate, wherein the portion of the first work function layer has a smaller thickness than a thickness of the first work function layer.Type: ApplicationFiled: June 15, 2016Publication date: November 16, 2017Inventors: Po-Wen Su, Zhen Wu, Hsiao-Pang Chou, Chiu-Hsien Yeh, Shui-Yen Lu, Jian-Wei Chen
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Publication number: 20170294523Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first organic layer on the substrate; patterning the first organic layer to form an opening; forming a second organic layer in the opening; and removing the first organic layer to form a patterned second organic layer on the substrate.Type: ApplicationFiled: April 10, 2016Publication date: October 12, 2017Inventors: Zhen Wu, Chiu-Hsien Yeh, Po-Wen Su, Kuan-Ying Lai
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Patent number: 9685383Abstract: A method of forming a semiconductor device includes following steps. First of all, a first work function layer is formed on a substrate. Next, a first patterned photoresist layer is formed on the first work function layer. Then, the first work function layer is partially removed by using the first patterned photoresist layer as a mask to form a patterned first work function layer. Subsequently, the first patterned photoresist layer is removed by providing radical oxygen.Type: GrantFiled: May 13, 2015Date of Patent: June 20, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chiu-Hsien Yeh, Zhen Wu, Yen-Cheng Chang, Yu-Ting Tseng
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Publication number: 20160336194Abstract: A method of forming a semiconductor device includes following steps. First of all, a first work function layer is formed on a substrate. Next, a first patterned photoresist layer is formed on the first work function layer. Then, the first work function layer is partially removed by using the first patterned photoresist layer as a mask to form a patterned first work function layer. Subsequently, the first patterned photoresist layer is removed by providing radical oxygen.Type: ApplicationFiled: May 13, 2015Publication date: November 17, 2016Inventors: Chiu-Hsien Yeh, Zhen Wu, Yen-Cheng Chang, Yu-Ting Tseng
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Patent number: 9312258Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.Type: GrantFiled: July 8, 2013Date of Patent: April 12, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Guang-Yaw Hwang, Ling-Chun Chou, I-Chang Wang, Shin-Chuan Huang, Jiunn-Hsiung Liao, Shin-Chi Chen, Pau-Chung Lin, Chiu-Hsien Yeh, Chin-Cheng Chien, Chieh-Te Chen
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Patent number: 9281201Abstract: A method of manufacturing a semiconductor device having a metal gate is provided. A substrate having a first conductive type transistor and a second conductive type transistor formed thereon is provided. The first conductive type transistor has a first trench and the second conductive type transistor has a second trench. A first work function layer is formed in the first trench. A hardening process is performed for the first work function layer. A softening process is performed for a portion of the first work function layer. A pull back step is performed to remove the portion of the first work function layer. A second work function layer is formed in the second trench. A low resistive metal layer is formed in the first trench and the second trench.Type: GrantFiled: September 18, 2013Date of Patent: March 8, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ted Ming-Lang Guo, Chiu-Hsien Yeh, Chin-Cheng Chien, Chun-Yuan Wu
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Patent number: 9000568Abstract: A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure.Type: GrantFiled: September 26, 2011Date of Patent: April 7, 2015Assignee: United Microelectronics Corp.Inventors: Szu-Hao Lai, Yu-Ren Wang, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh, Te-Lin Sun
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Patent number: 8987096Abstract: A semiconductor process includes the following steps. A substrate is provided. An ozone saturated deionized water process is performed to form an oxide layer on the substrate. A dielectric layer is formed on the oxide layer. A post dielectric annealing (PDA) process is performed on the dielectric layer and the oxide layer.Type: GrantFiled: February 7, 2012Date of Patent: March 24, 2015Assignee: United Microelectronics Corp.Inventors: Ying-Tsung Chen, Chien-Ting Lin, Ssu-I Fu, Shih-Hung Tsai, Wen-Tai Chiang, Chih-Wei Chen, Chiu-Hsien Yeh, Shao-Wei Wang, Kai-Ping Wang
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Publication number: 20150079777Abstract: A method of manufacturing a semiconductor device having a metal gate is provided. A substrate having a first conductive type transistor and a second conductive type transistor formed thereon is provided. The first conductive type transistor has a first trench and the second conductive type transistor has a second trench. A first work function layer is formed in the first trench. A hardening process is performed for the first work function layer. A softening process is performed for a portion of the first work function layer. A pull back step is performed to remove the portion of the first work function layer. A second work function layer is formed in the second trench. A low resistive metal layer is formed in the first trench and the second trench.Type: ApplicationFiled: September 18, 2013Publication date: March 19, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ted Ming-Lang Guo, Chiu-Hsien Yeh, Chin-Cheng Chien, Chun-Yuan Wu
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Patent number: 8981527Abstract: A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.Type: GrantFiled: August 23, 2011Date of Patent: March 17, 2015Assignee: United Microelectronics Corp.Inventors: Jie-Ning Yang, Shih-Chieh Hsu, Yao-Chang Wang, Chi-Horn Pai, Chi-Sheng Tseng, Kun-Szu Tseng, Ying-Hung Chou, Chiu-Hsien Yeh
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Patent number: 8980753Abstract: A method for fabricating a metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a first metal-oxide semiconductor (MOS) transistor on the first transistor region and a second MOS transistor on the second transistor region, in which the first MOS transistor includes a first dummy gate and the second MOS transistor comprises a second dummy gate; forming a patterned hard mask on the second MOS transistor, in which the hard mask includes at least one metal atom; and using the patterned hard mask to remove the first dummy gate of the first MOS transistor.Type: GrantFiled: September 21, 2010Date of Patent: March 17, 2015Assignee: United Mircroelectronics Corp.Inventors: Yeng-Peng Wang, Chun-Hsien Lin, Chiu-Hsien Yeh, Chin-Cheng Chien, Chan-Lon Yang