Patents by Inventor Chiu-Hsien Yeh

Chiu-Hsien Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240102561
    Abstract: A proportional valve includes a casing and a valve trim. The casing has at least one fluid inlet, a fluid outlet, at least one first connection passageway, at least one second connection passageway and an accommodating space. The first connection passageway is connected with the fluid inlet. The second connection passageway is connected with the fluid outlet. The valve trim is located in the accommodating space, including a flow splitter an adjusting rotor. The flow splitter has at least one third connection passageway and at least one fourth connection passageway. The third connection passageway is connected with the first connection passageway. The fourth connection passageway is connected with the second connection passageway. The adjusting rotor has a channel and at least one blocking portion. The adjusting rotor is rotatably disposed on the flow splitter so that the blocking portion blocks a part of the third connection passageway.
    Type: Application
    Filed: November 3, 2022
    Publication date: March 28, 2024
    Applicant: COOLER MASTER CO., LTD.
    Inventors: Chiu Yu YEH, Wen-Hsien LIN, Wen-Hung CHEN
  • Patent number: 10290736
    Abstract: A semiconductor device and a method of forming the same are provided. A substrate is provided. A trench is formed in the substrate and a conductive material is formed filling the trench. A portion of the conductive material filling an upper portion of the trench is removed to expose an upper surface of the substrate and an upper corner and an upper sidewall of the trench. A doping process is performed to form a doped region in the substrate along the exposed upper surface of the substrate and the exposed upper corner and upper sidewall of the trench. The doped region has an upside-down L shape.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: May 14, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Kai-Ping Chen, Li-Wei Feng, Kuei-Hsuan Yu, Chiu-Hsien Yeh
  • Patent number: 10157744
    Abstract: A method for forming patterns of semiconductor device is provided in the present invention, with steps of filling up first self-assembly material in first openings in a dielectric layer, phase-separating the first self-assembly material to form a first portion and a second portion surrounding the first portion, removing the first portion and performing a first etch process to form a first mask pattern in a mask layer, forming a second dielectric layer and repeating the above steps to form a second mask pattern in the mask layer, wherein the second mask pattern is aligned with the first mask pattern to form a common mask pattern.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: December 18, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Kai-Ping Chen, Kuei-Hsuan Yu, Chiu-Hsien Yeh, Li-Wei Feng
  • Patent number: 10151048
    Abstract: A manufacturing method of an epitaxial contact structure in a semiconductor memory device includes the following steps. A recess is formed in a semiconductor substrate by an etching process. An etching defect is formed in the recess by the etching process. An oxidation process is performed after the etching process. An oxide layer is formed in the recess by the oxidation process, and the etching defect is encompassed by the oxide layer. A cleaning process is performed after the oxidation process. The oxide layer and the etching defect encompassed by the oxide layer are removed by the cleaning process. An epitaxial growth process is performed to form an epitaxial contact structure in the recess after the cleaning process.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: December 11, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Wan-Chi Wu, Hui-Ling Chuang, Chih-Chi Cheng, Chiu-Hsien Yeh, Chien-Cheng Tsai, Hung-Jung Yan
  • Publication number: 20180226251
    Abstract: A method for forming patterns of semiconductor device is provided in the present invention, with steps of filling up first self-assembly material in first openings in a dielectric layer, phase-separating the first self-assembly material to form a first portion and a second portion surrounding the first portion, removing the first portion and performing a first etch process to form a first mask pattern in a mask layer, forming a second dielectric layer and repeating the above steps to form a second mask pattern in the mask layer, wherein the second mask pattern is aligned with the first mask pattern to form a common mask pattern.
    Type: Application
    Filed: February 1, 2018
    Publication date: August 9, 2018
    Inventors: Kai-Ping Chen, Kuei-Hsuan Yu, Chiu-Hsien Yeh, Li-Wei Feng
  • Patent number: 10043882
    Abstract: A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. A barrier layer is then formed on the first region of the substrate. A first work function layer is formed on the barrier layer. An upper half portion of the first work function layer is converted into a non-volatile material layer. The non-volatile material layer is removed and a lower half portion of the first work function layer is kept.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: August 7, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Zhen Wu, Hsiao-Pang Chou, Chiu-Hsien Yeh, Shui-Yen Lu, Jian-Wei Chen
  • Publication number: 20180212055
    Abstract: A semiconductor device and a method of forming the same are provided. A substrate is provided. A trench is formed in the substrate and a conductive material is formed filling the trench. A portion of the conductive material filling an upper portion of the trench is removed to expose an upper surface of the substrate and an upper corner and an upper sidewall of the trench. A doping process is performed to form a doped region in the substrate along the exposed upper surface of the substrate and the exposed upper corner and upper sidewall of the trench. The doped region has an upside-down L shape.
    Type: Application
    Filed: January 17, 2018
    Publication date: July 26, 2018
    Inventors: Kai-Ping Chen, Li-Wei Feng, Kuei-Hsuan Yu, Chiu-Hsien Yeh
  • Patent number: 10026827
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first organic layer on the substrate; patterning the first organic layer to form an opening; forming a second organic layer in the opening; and removing the first organic layer to form a patterned second organic layer on the substrate.
    Type: Grant
    Filed: April 10, 2016
    Date of Patent: July 17, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhen Wu, Chiu-Hsien Yeh, Po-Wen Su, Kuan-Ying Lai
  • Publication number: 20180151685
    Abstract: A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. A barrier layer is then formed on the first region of the substrate. A first work function layer is formed on the barrier layer. An upper half portion of the first work function layer is converted into a non-volatile material layer. The non-volatile material layer is removed and a lower half portion of the first work function layer is kept.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 31, 2018
    Inventors: Po-Wen Su, Zhen Wu, Hsiao-Pang Chou, Chiu-Hsien Yeh, Shui-Yen Lu, Jian-Wei Chen
  • Patent number: 9899491
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a conductive layer stacked one over another on the substrate. The second gate structure includes the barrier layer, a portion of the first work function layer and the conductive layer stacked one over another on the substrate, wherein the portion of the first work function layer has a smaller thickness than a thickness of the first work function layer.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: February 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Zhen Wu, Hsiao-Pang Chou, Chiu-Hsien Yeh, Shui-Yen Lu, Jian-Wei Chen
  • Publication number: 20170330952
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a conductive layer stacked one over another on the substrate. The second gate structure includes the barrier layer, a portion of the first work function layer and the conductive layer stacked one over another on the substrate, wherein the portion of the first work function layer has a smaller thickness than a thickness of the first work function layer.
    Type: Application
    Filed: June 15, 2016
    Publication date: November 16, 2017
    Inventors: Po-Wen Su, Zhen Wu, Hsiao-Pang Chou, Chiu-Hsien Yeh, Shui-Yen Lu, Jian-Wei Chen
  • Publication number: 20170294523
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first organic layer on the substrate; patterning the first organic layer to form an opening; forming a second organic layer in the opening; and removing the first organic layer to form a patterned second organic layer on the substrate.
    Type: Application
    Filed: April 10, 2016
    Publication date: October 12, 2017
    Inventors: Zhen Wu, Chiu-Hsien Yeh, Po-Wen Su, Kuan-Ying Lai
  • Patent number: 9685383
    Abstract: A method of forming a semiconductor device includes following steps. First of all, a first work function layer is formed on a substrate. Next, a first patterned photoresist layer is formed on the first work function layer. Then, the first work function layer is partially removed by using the first patterned photoresist layer as a mask to form a patterned first work function layer. Subsequently, the first patterned photoresist layer is removed by providing radical oxygen.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: June 20, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chiu-Hsien Yeh, Zhen Wu, Yen-Cheng Chang, Yu-Ting Tseng
  • Publication number: 20160336194
    Abstract: A method of forming a semiconductor device includes following steps. First of all, a first work function layer is formed on a substrate. Next, a first patterned photoresist layer is formed on the first work function layer. Then, the first work function layer is partially removed by using the first patterned photoresist layer as a mask to form a patterned first work function layer. Subsequently, the first patterned photoresist layer is removed by providing radical oxygen.
    Type: Application
    Filed: May 13, 2015
    Publication date: November 17, 2016
    Inventors: Chiu-Hsien Yeh, Zhen Wu, Yen-Cheng Chang, Yu-Ting Tseng
  • Patent number: 9312258
    Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: April 12, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Guang-Yaw Hwang, Ling-Chun Chou, I-Chang Wang, Shin-Chuan Huang, Jiunn-Hsiung Liao, Shin-Chi Chen, Pau-Chung Lin, Chiu-Hsien Yeh, Chin-Cheng Chien, Chieh-Te Chen
  • Patent number: 9281201
    Abstract: A method of manufacturing a semiconductor device having a metal gate is provided. A substrate having a first conductive type transistor and a second conductive type transistor formed thereon is provided. The first conductive type transistor has a first trench and the second conductive type transistor has a second trench. A first work function layer is formed in the first trench. A hardening process is performed for the first work function layer. A softening process is performed for a portion of the first work function layer. A pull back step is performed to remove the portion of the first work function layer. A second work function layer is formed in the second trench. A low resistive metal layer is formed in the first trench and the second trench.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: March 8, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ted Ming-Lang Guo, Chiu-Hsien Yeh, Chin-Cheng Chien, Chun-Yuan Wu
  • Patent number: 9000568
    Abstract: A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: April 7, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Szu-Hao Lai, Yu-Ren Wang, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh, Te-Lin Sun
  • Patent number: 8987096
    Abstract: A semiconductor process includes the following steps. A substrate is provided. An ozone saturated deionized water process is performed to form an oxide layer on the substrate. A dielectric layer is formed on the oxide layer. A post dielectric annealing (PDA) process is performed on the dielectric layer and the oxide layer.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: March 24, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Ying-Tsung Chen, Chien-Ting Lin, Ssu-I Fu, Shih-Hung Tsai, Wen-Tai Chiang, Chih-Wei Chen, Chiu-Hsien Yeh, Shao-Wei Wang, Kai-Ping Wang
  • Publication number: 20150079777
    Abstract: A method of manufacturing a semiconductor device having a metal gate is provided. A substrate having a first conductive type transistor and a second conductive type transistor formed thereon is provided. The first conductive type transistor has a first trench and the second conductive type transistor has a second trench. A first work function layer is formed in the first trench. A hardening process is performed for the first work function layer. A softening process is performed for a portion of the first work function layer. A pull back step is performed to remove the portion of the first work function layer. A second work function layer is formed in the second trench. A low resistive metal layer is formed in the first trench and the second trench.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 19, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ted Ming-Lang Guo, Chiu-Hsien Yeh, Chin-Cheng Chien, Chun-Yuan Wu
  • Patent number: 8981527
    Abstract: A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: March 17, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Jie-Ning Yang, Shih-Chieh Hsu, Yao-Chang Wang, Chi-Horn Pai, Chi-Sheng Tseng, Kun-Szu Tseng, Ying-Hung Chou, Chiu-Hsien Yeh