Patents by Inventor Chiu-Hua Chung
Chiu-Hua Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230343816Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.Type: ApplicationFiled: June 28, 2023Publication date: October 26, 2023Inventors: Hong-Yang CHEN, Tian Sheng Lin, Yi-Cheng Chiu, Hung-Chou Lin, Yi-Min Chen, Kuo-Ming Wu, Chiu-Hua Chung
-
Publication number: 20230324787Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.Type: ApplicationFiled: June 15, 2023Publication date: October 12, 2023Inventors: Kuo-Hao LEE, You-Cheng JHANG, Han-Zong PAN, Jui-Chun WENG, Chiu-Hua CHUNG, Sheng-Yuan LIN, Hsin-Yu CHEN
-
Patent number: 11728374Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.Type: GrantFiled: October 11, 2021Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hong-Yang Chen, Tian Sheng Lin, Yi-Cheng Chiu, Hung-Chou Lin, Yi-Min Chen, Kuo-Ming Wu, Chiu-Hua Chung
-
Patent number: 11726401Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.Type: GrantFiled: July 27, 2022Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Hao Lee, You-Cheng Jhang, Han-Zong Pan, Jui-Chun Weng, Chiu-Hua Chung, Sheng-Yuan Lin, Hsin-Yu Chen
-
Publication number: 20230207642Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.Type: ApplicationFiled: February 17, 2023Publication date: June 29, 2023Inventors: Yi-Cheng CHIU, Tian Sheng LIN, Hung-Chou LIN, Yi-Min CHEN, Chiu-Hua CHUNG
-
Patent number: 11688804Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a source region and a drain region in a substrate, a gate structure and a metallic line. The source region surrounds the drain region in the substrate. The gate structure is disposed on the substrate, and disposed between the source region and the drain region. The gate structure surrounds the drain region. The metallic line is located above the source and drain regions and the gate structure and electrically connected to the drain region or the source region. The source region includes a doped region having a break region located between two opposite ends of the doped region. The metallic line extends from the drain region, across the gate structure and across the break region and beyond the source region.Type: GrantFiled: March 4, 2021Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Cheng Chiu, Tien-Sheng Lin, Sheng-Fu Hsu, Chen-Yi Lee, Chiu-Hua Chung
-
Patent number: 11588028Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.Type: GrantFiled: January 15, 2021Date of Patent: February 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Cheng Chiu, Tian Sheng Lin, Hung-Chou Lin, Yi-Min Chen, Chiu-Hua Chung
-
Publication number: 20220365424Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Inventors: Kuo-Hao LEE, You-Cheng JHANG, Han-Zong PAN, Jui-Chun WENG, Chiu-Hua CHUNG, Sheng-Yuan LIN, Hsin-Yu CHEN
-
Patent number: 11415878Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.Type: GrantFiled: September 15, 2020Date of Patent: August 16, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Hao Lee, You-Cheng Jhang, Han-Zong Pan, Jui-Chun Weng, Chiu-Hua Chung, Sheng-Yuan Lin, Hsin-Yu Chen
-
Publication number: 20220231133Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.Type: ApplicationFiled: January 15, 2021Publication date: July 21, 2022Inventors: Yi-Cheng CHIU, Tian Sheng LIN, Hung-Chou LIN, Yi-Min CHEN, Chiu-Hua CHUNG
-
Publication number: 20220082931Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.Type: ApplicationFiled: September 15, 2020Publication date: March 17, 2022Inventors: Kuo-Hao LEE, You-Cheng JHANG, Han-Zong PAN, Jui-Chun WENG, Chiu-Hua CHUNG, Sheng-Yuan LIN, Hsin-Yu CHEN
-
Publication number: 20220069123Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a source region and a drain region in a substrate, a gate structure and a metallic line. The source region surrounds the drain region in the substrate. The gate structure is disposed on the substrate, and disposed between the source region and the drain region. The gate structure surrounds the drain region. The metallic line is located above the source and drain regions and the gate structure and electrically connected to the drain region or the source region. The source region includes a doped region having a break region located between two opposite ends of the doped region. The metallic line extends from the drain region, across the gate structure and across the break region and beyond the source region.Type: ApplicationFiled: March 4, 2021Publication date: March 3, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Cheng Chiu, Tien-Sheng Lin, Sheng-Fu Hsu, Chen-Yi Lee, Chiu-Hua Chung
-
Publication number: 20220028967Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.Type: ApplicationFiled: October 11, 2021Publication date: January 27, 2022Inventors: Hong-Yang CHEN, Tian Sheng LIN, Yi-Cheng CHIU, Hung-Chou LIN, Yi-Min CHEN, Kuo-Ming WU, Chiu-Hua CHUNG
-
Patent number: 11145709Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.Type: GrantFiled: June 12, 2019Date of Patent: October 12, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hong-Yang Chen, Tian Sheng Lin, Yi-Cheng Chiu, Hung-Chou Lin, Yi-Min Chen, Kuo-Ming Wu, Chiu-Hua Chung
-
Publication number: 20210313416Abstract: The present disclosure relates to a semiconductor structure. The semiconductor structure includes a lower electrode over a substrate, a first capacitor dielectric layer over the lower electrode, an intermediate electrode over the first capacitor dielectric layer, and a second capacitor dielectric layer is over the intermediate electrode. An upper electrode is over the second capacitor dielectric layer. The upper electrode is completely confined over the intermediate electrode. A first protection layer is completely confined over the intermediate electrode. The first protection layer covers opposing sidewalls of the upper electrode and upper surfaces of the intermediate electrode and the upper electrode.Type: ApplicationFiled: June 17, 2021Publication date: October 7, 2021Inventors: Guo-Jyun Luo, Chen-Chien Chang, Chiu-Hua Chung, Shiuan-Jeng Lin, Han-Zong Pan
-
Patent number: 10879236Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.Type: GrantFiled: October 24, 2019Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Karthick Murukesan, Wen-Chih Chiang, Chiu-Hua Chung, Chun Lin Tsai, Kuo-Ming Wu, Shiuan-Jeng Lin, Tien Sheng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
-
Patent number: 10866276Abstract: A method for probe card alignment is provided. The method includes providing a probe card with a plurality of probe needles having their distal ends on a reference plane. The method further includes providing a light from both the upper side and lower side of the reference plane. The method also includes using a camera to image the probe needles. In addition, the method includes performing a probe card alignment process according to the image generated by the camera.Type: GrantFiled: December 10, 2019Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Kai-Di Chuang, Tien-Chung Lee, Chiu-Hua Chung, Kang-Tai Peng
-
Publication number: 20200373380Abstract: The present disclosure relates to a semiconductor device structure. The semiconductor device structure has a first conductive layer disposed over a substrate and a first capacitor dielectric layer comprising a first dielectric material disposed over the first conductive layer. A second conductive layer is over the first capacitor dielectric layer, a second capacitor dielectric layer comprising a second dielectric material is disposed over the second conductive layer, and a third conductive layer is over the second capacitor dielectric layer. A first barrier layer is disposed between an upper surface of the first conductive layer and a lower surface of the first capacitor dielectric layer.Type: ApplicationFiled: August 12, 2020Publication date: November 26, 2020Inventors: Guo-Jyun Luo, Chen-Chien Chang, Chiu-Hua Chung, Shiuan-Jeng Lin, Han-Zong Pan
-
Patent number: 10748986Abstract: A semiconductor device structure and the formation method thereof are provided. The semiconductor device structure includes a semiconductor substrate and a first capacitor and a second capacitor over the semiconductor substrate. The first capacitor has a first capacitor dielectric layer, and the second capacitor has a second capacitor dielectric layer. The first capacitor dielectric layer is between the second capacitor dielectric layer and the semiconductor substrate. The first capacitor and the second capacitor are electrically connected in parallel. The first capacitor has a first linear temperature coefficient and a first quadratic voltage coefficient. The second capacitor has a second linear temperature coefficient and a second quadratic voltage coefficient. One or both of a first ratio of the first linear temperature coefficient to the second linear temperature coefficient and a second ratio of the first quadratic voltage coefficient to the second quadratic voltage coefficient is negative.Type: GrantFiled: March 29, 2018Date of Patent: August 18, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Guo-Jyun Luo, Shiuan-Jeng Lin, Chiu-Hua Chung, Chen-Chien Chang, Han-Zong Pan
-
Patent number: 10679987Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.Type: GrantFiled: September 12, 2018Date of Patent: June 9, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Karthick Murukesan, Wen-Chih Chiang, Chiu-Hua Chung, Chun Lin Tsai, Kuo-Ming Wu, Shiuan-Jeng Lin, Tien Sheng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu