Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

Abstract: A semiconductor device includes a substrate having a magnetic random access memory (MRAM) region and a logic region, a first metal interconnection on the MRAM region, a second metal interconnection on the logic region, a stop layer extending from the first metal interconnection to the second metal interconnection, and a magnetic tunneling junction (MTJ) on the first metal interconnection. Preferably, the stop layer on the first metal interconnection and the stop layer on the second metal interconnection have different thicknesses.

Abstract: A semiconductor structure includes an electrode element with an upper surface. The upper surface includes at least one convex curved portion.

Abstract: A semiconductor device includes a substrate having a magnetic random access memory (MRAM) region and a logic region, a first metal interconnection on the MRAM region, a second metal interconnection on the logic region, a stop layer extending from the first metal interconnection to the second metal interconnection, and a magnetic tunneling junction (MTJ) on the first metal interconnection. Preferably, the stop layer on the first metal interconnection and the stop layer on the second metal interconnection have different thicknesses.

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

Abstract: A MRAM includes a plurality of memory cells, an operation unit, a voltage generator, and an input/output circuit. The operation unit includes multiple groups of memory cells among the plurality of memory cells. The voltage generator is configured to provide a plurality of control signals by voltage-dividing a voltage control signal and selectively output the plurality of control signals to the input/output circuit. The input/output circuit is configured to output a plurality of switching pulse signals to the multiple groups of memory cells according to the plurality of control signals, wherein each switching pulse signal differs in pulse width or level.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the MTJ, and a second spacer on another side of the MTJ, in which the first spacer and the second spacer are asymmetric. Specifically, the MTJ further includes a first bottom electrode disposed on a metal interconnection, a capping layer on the bottom electrode, and a top electrode on the capping layer, in which a top surface of the first spacer is even with a top surface of the top electrode and a top surface of the second spacer is lower than the top surface of the top electrode and higher than the top surface of the capping layer.

Abstract: A circuit selector of embedded magnetoresistive random access memory (EMRAM) includes a transistor comprising a source/drain terminal coupled to a first magnetic tunneling junction (MTJ) and a second MTJ, a gate terminal, and a drain/source terminal coupled to a voltage source. Preferably, the first MTJ includes a first free layer, a first barrier layer, and a first pinned layer, in which the first free layer is coupled to the source/drain terminal and the first pinned layer is coupled to a first circuit. The second MTJ includes a second free layer, a second barrier layer, and a second pinned layer, in which the second pinned layer is coupled to the source/drain terminal and the second free layer is coupled to a second circuit.

Abstract: A semiconductor structure includes an electrode element with an upper surface. The upper surface includes at least one convex curved portion.

Abstract: A circuit selector of embedded magnetoresistive random access memory (EMRAM) includes a transistor comprising a source/drain terminal coupled to a first magnetic tunneling junction (MTJ) and a second MTJ, a gate terminal, and a drain/source terminal coupled to a voltage source. Preferably, the first MTJ includes a first free layer, a first barrier layer, and a first pinned layer, in which the first free layer is coupled to the source/drain terminal and the first pinned layer is coupled to a first circuit. The second MTJ includes a second free layer, a second barrier layer, and a second pinned layer, in which the second pinned layer is coupled to the source/drain terminal and the second free layer is coupled to a second circuit.

Abstract: A magnetoresistive memory cell is provided including a substrate. An inter-layer dielectric layer is disposed on the substrate. A via structure is disposed in the inter-layer dielectric layer. A magnetic pinned layer is disposed on the via structure. A tunnel barrier layer is disposed on the magnetic pinned layer to cover a top and a sidewall of the magnetic pinned layer, wherein the tunnel barrier layer comprises a horizontal extending portion outward from a bottom of the sidewall. A magnetic free layer with a -like structure is disposed on the tunnel barrier layer, wherein the magnetic free layer is isolated from the magnetic pinned layer by the tunnel bather layer. A spacer is disposed on the sidewall of the magnetic free layer. The spacer extends to the inter-layer dielectric layer.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the MTJ, and a second spacer on another side of the MTJ, in which the first spacer and the second spacer are asymmetric. Specifically, the MTJ further includes a first bottom electrode disposed on a metal interconnection, a capping layer on the bottom electrode, and a top electrode on the capping layer, in which a top surface of the first spacer is even with a top surface of the top electrode and a top surface of the second spacer is lower than the top surface of the top electrode and higher than the top surface of the capping layer.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the MTJ, and a second spacer on another side of the MTJ, wherein the first spacer and the second spacer are asymmetric. Specifically, the MTJ further includes a first bottom electrode disposed on a metal interconnection, a capping layer on the bottom electrode, and a top electrode on the capping layer, in which a top surface of the first spacer is even with a top surface of the top electrode and a top surface of the second spacer is lower than the top surface of the top electrode and higher than the top surface of the capping layer.

Abstract: A magnetoresistance device is disclosed, comprising a bottom electrode, a magnetic tunneling junction (MTJ) disposed on the bottom electrode, a top electrode disposed on the magnetic tunneling junction, a first spacer disposed on the magnetic tunneling junction and covering a sidewall of the top electrode, and a second spacer disposed on the first spacer and conformally covering along a sidewall of the first spacer, a sidewall of the magnetic tunneling junction and a sidewall of the bottom electrode.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the MTJ, and a second spacer on another side of the MTJ, wherein the first spacer and the second spacer are asymmetric. Specifically, the MTJ further includes a first bottom electrode disposed on a metal interconnection, a capping layer on the bottom electrode, and a top electrode on the capping layer, in which a top surface of the first spacer is even with a top surface of the top electrode and a top surface of the second spacer is lower than the top surface of the top electrode and higher than the top surface of the capping layer.

Abstract: A magnetoresistance device is disclosed, comprising a bottom electrode, a magnetic tunneling junction (MTJ) disposed on the bottom electrode, a top electrode disposed on the magnetic tunneling junction, a first spacer disposed on the magnetic tunneling junction and covering a sidewall of the top electrode, and a second spacer disposed on the first spacer and conformally covering along a sidewall of the first spacer, a sidewall of the magnetic tunneling junction and a sidewall of the bottom electrode.

Abstract: A magnetoresistive memory cell is provided including a substrate. An inter-layer dielectric layer is disposed on the substrate. A via structure is disposed in the inter-layer dielectric layer. A magnetic pinned layer is disposed on the via structure. A tunnel barrier layer is disposed on the magnetic pinned layer to cover a top and a sidewall of the magnetic pinned layer, wherein the tunnel barrier layer comprises a horizontal extending portion outward from a bottom of the sidewall. A magnetic free layer with a -like structure is disposed on the tunnel barrier layer, wherein the magnetic free layer is isolated from the magnetic pinned layer by the tunnel bather layer. A spacer is disposed on the sidewall of the magnetic free layer. The spacer extends to the inter-layer dielectric layer.