Patents by Inventor Chiu-Sheng Ho

Chiu-Sheng Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10707305
    Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: July 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Guo Chen, Kun-Yuan Wu, Tai-You Chen, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo
  • Publication number: 20190214463
    Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.
    Type: Application
    Filed: March 14, 2019
    Publication date: July 11, 2019
    Inventors: Cheng-Guo Chen, Kun-Yuan Wu, Tai-You Chen, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo
  • Patent number: 10276663
    Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: April 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Guo Chen, Kun-Yuan Wu, Tai-You Chen, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo
  • Publication number: 20180122705
    Abstract: First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ILD) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. Next, a first metal gate is formed on the first region and a second metal gate is formed on the second region.
    Type: Application
    Filed: November 2, 2016
    Publication date: May 3, 2018
    Inventors: Tai-You Chen, Cheng-Guo Chen, Kun-Yuan Wu, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo, Shang-Jr Chen
  • Patent number: 9960083
    Abstract: First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ILD) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. Next, a first metal gate is formed on the first region and a second metal gate is formed on the second region.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: May 1, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-You Chen, Cheng-Guo Chen, Kun-Yuan Wu, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo, Shang-Jr Chen
  • Publication number: 20180019341
    Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.
    Type: Application
    Filed: July 18, 2016
    Publication date: January 18, 2018
    Inventors: Cheng-Guo Chen, Kun-Yuan Wu, Tai-You Chen, Chiu-Sheng Ho, Po-Kang Yang, Ta-Kang Lo