Patents by Inventor Chiukin (Steven) Lai

Chiukin (Steven) Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240047269
    Abstract: Provided are deposition processes including deposition of a thin, protective Mo layer using a molybdenum chloride (MoClx) precursor. This may be followed by Mo deposition to fill the feature using a molybdenum oxyhalide (MoOyXz) precursor. The protective Mo layer enables Mo fill using an MoOyXz precursor without oxidation of the underlying surfaces. Also provided are in-situ clean processes in which a MoClx precursor is used to remove oxidation from underlying surfaces prior to deposition. Subsequent deposition using the MoClx precursor may deposit an initial layer and/or fill a feature.
    Type: Application
    Filed: January 3, 2022
    Publication date: February 8, 2024
    Inventors: Jeong-Seok NA, Shruti Vivek THOMBARE, Yao-Tsung HSIEH, David Joseph MANDIA, Chiukin Steven LAI
  • Publication number: 20230326790
    Abstract: Methods of filling features including metal and dielectric surfaces with conductive materials involve cleaning the metal surfaces with little or no damage to the dielectric surfaces. After cleaning, the feature may be exposed to one or more reactants to fill the feature with the conductive material in an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process. Deposition may be selective or non-selective to the metal surface. In some embodiments, the filled feature is barrier-less, such that the conductive material directly contacts the metal and dielectric surfaces with no interposing barrier or adhesion layer.
    Type: Application
    Filed: May 21, 2021
    Publication date: October 12, 2023
    Applicant: Lam Research Corporation
    Inventors: Raihan M. TARAFDAR, Chiukin Steven LAI, Jeong-Seok NA
  • Publication number: 20220328317
    Abstract: Provided are methods of filling patterned features with molybdenum (Mo). The methods involve selective deposition of Mo films on bottom metal-containing surfaces of a feature including dielectric sidewalls. The selective growth of Mo on the bottom surface allows bottom-up growth and high quality, void-free fill. Also provided are related apparatus.
    Type: Application
    Filed: September 1, 2020
    Publication date: October 13, 2022
    Applicant: Lam Research Corporation
    Inventors: Jeong-Seok NA, Yao-Tsung HSIEH, Chiukin Steven LAI, Patrick A. VAN CLEEMPUT
  • Publication number: 20220298624
    Abstract: Substantially carbon-free molybdenum-containing and tungsten-containing films are deposited on semiconductor substrates using halide-free metalorganic precursors. The precursors do not include metal-carbon bonds, carbonyl ligands, and, preferably do not include beta-hydrogen atoms. Metal-containing films, such as molybdenum nitride, molybdenum oxynitride, molybdenum silicide, and molybdenum boride with carbon content of less than about 5% atomic, such as less than about 3% atomic are deposited. The films are deposited in some embodiments by reacting the metal-containing precursor with a reactant on a surface of a substrate in an absence of plasma, e.g. using several ALD cycles. In some embodiments the formed film is then treated with a second reactant in a plasma to modify its properties (e.g., to densify the film, to reduce resistivity of the film, or to increase its work function). The films can be used as liners, diffusion barriers, and as electrode material in pMOS devices.
    Type: Application
    Filed: August 10, 2020
    Publication date: September 22, 2022
    Inventors: Kyle Jordan Blakeney, Chiukin Steven Lai, Thomas M. Pratt, Eric H. Lenz, Jason Stevens
  • Publication number: 20220223471
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Application
    Filed: January 31, 2022
    Publication date: July 14, 2022
    Inventors: Shruti Vivek THOMBARE, Raashina HUMAYUN, Michal DANEK, Chiukin Steven LAI, Joshua COLLINS, Hanna BAMNOLKER, Griffin John KENNEDY, Gorun BUTAIL, Patrick A. van Cleemput
  • Publication number: 20220115244
    Abstract: Methods of depositing tungsten into high aspect ratio features using a dep-etch-dep process integrating various deposition techniques with alternating pulses of surface modification and removal during etch are provided herein.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventors: Chiukin Steven LAI, Keren Jacobs KANARIK, Samantha S.H. TAN, Anand CHANDRASHEKAR, Teh-Tien SU, Wenbing YANG, Michael WOOD, Michal DANEK
  • Publication number: 20210305059
    Abstract: Methods of depositing tungsten into high aspect ratio features using a dep-etch-dep process integrating various deposition techniques with alternating pulses of surface modification and removal during etch are provided herein.
    Type: Application
    Filed: June 15, 2021
    Publication date: September 30, 2021
    Inventors: Chiukin Steven Lai, Keren Jacobs Kanarik, Samantha Tan, Anand Chandrashekar, Teh-Tien Su, Wenbing Yang, Michael Wood, Michal Danek
  • Patent number: 11069535
    Abstract: Methods of depositing tungsten into high aspect ratio features using a dep-etch-dep process integrating various deposition techniques with alternating pulses of surface modification and removal during etch are provided herein.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: July 20, 2021
    Assignee: Lam Research Corporation
    Inventors: Chiukin Steven Lai, Keren Jacobs Kanarik, Samantha Tan, Anand Chandrashekar, Teh-Tien Su, Wenbing Yang, Michael Wood, Michal Danek
  • Publication number: 20200365456
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 19, 2020
    Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick van Cleemput
  • Patent number: 10777453
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: September 15, 2020
    Assignee: Lam Research Corporation
    Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput
  • Publication number: 20200286743
    Abstract: Methods of depositing tungsten into high aspect ratio features using a dep-etch-dep process integrating various deposition techniques with alternating pulses of surface modification and removal during etch are provided herein.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: Chiukin Steven Lai, Keren Jacobs Kanarik, Samantha Tan, Anand Chandrashekar, Teh-Tien Su, Wenbing Yang, Michael Wood, Michal Danek
  • Patent number: 10731250
    Abstract: In some embodiments, deposition processes for ruthenium (Ru) feature fill include deposition of a thin, protective Ru film under reducing conditions, followed by a Ru fill step under oxidizing conditions. The presence of protective Ru films formed under oxygen-free conditions or with an oxygen-removing operation can enable Ru fill without oxidation of an underlying adhesion layer or metal feature.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: August 4, 2020
    Assignee: Lam Research Corporation
    Inventors: Do Young Kim, Jeong-Seok Na, Chiukin Steven Lai, Raashina Humayun, Michal Danek
  • Publication number: 20200075403
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Application
    Filed: November 6, 2019
    Publication date: March 5, 2020
    Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput
  • Patent number: 10510590
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: December 17, 2019
    Assignee: Lam Research Corporation
    Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput
  • Patent number: 10438847
    Abstract: Provided herein are methods of forming conductive cobalt (Co) interconnects and Co features. The methods involve deposition of a thin manganese (Mn)-containing film on a dielectric followed by subsequent deposition of cobalt on the Mn-containing film. The Mn-containing film may be deposited on a silicon-containing dielectric, such as silicon dioxide, and annealed to form a manganese silicate.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: October 8, 2019
    Assignee: Lam Research Corporation
    Inventors: Chiukin Steven Lai, Jeong-Seok Na, Raashina Humayun, Michal Danek, Kaihan Abidi Ashtiani
  • Patent number: 10283404
    Abstract: Provided are methods of forming diffusion barriers and adhesion layers for interconnects such as cobalt (Co) interconnects or ruthenium (Ru) interconnects. The methods involve selective deposition of tungsten carbon nitride (WCN) films on the oxide surfaces of a feature including a Co surface. The selective growth of WCN on oxide allows the contact resistance at an interface such as a Co—Co interface or a Co—Ru interface to be significantly reduced while maintaining good film coverage, adhesion, and/or barrier properties on the sidewall oxide surfaces.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 7, 2019
    Assignee: Lam Research Corporation
    Inventors: Jeong-Seok Na, Megha Rathod, Chiukin Steven Lai, Raashina Humayun
  • Patent number: 10229826
    Abstract: A method for depositing a metal layer on a barrier layer includes a) arranging a substrate in a processing chamber. The substrate has been exposed to at least one of air and/or oxidizing chemistry and includes a barrier layer and one or more underlying layers, wherein the barrier layer includes a material selected from a group consisting of tantalum nitride, titanium nitride, tantalum and titanium. The method includes b) supplying a gas selected from a group consisting of hydrazine, a gas including fluorine species, a gas including chlorine species, derivatives of hydrazine, ammonia, carbon monoxide, a gas including amidinates, and/or a gas including metal organic ligands to the processing chamber for a predetermined period to remove oxidation from the barrier layer. The method includes c) depositing a metal layer on the barrier layer after b). The metal layer includes a metal selected from a group consisting of cobalt, copper, tungsten, ruthenium, rhodium, molybdenum, and nickel.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: March 12, 2019
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Raihan Tarafdar, Shruti Thombare, Jeong-Seok Na, Raashina Humayun, Chiukin Steven Lai
  • Publication number: 20180347041
    Abstract: Provided are deposition processes for ruthenium (Ru) feature fill. In some embodiments, the processes include deposition of a thin, protective Ru film under reducing conditions, followed by a Ru fill step under oxidizing conditions. The presence of protective Ru films formed under oxygen-free conditions or with an oxygen-removing operation can enable Ru fill without oxidation of an underlying adhesion layer or metal feature.
    Type: Application
    Filed: June 4, 2018
    Publication date: December 6, 2018
    Inventors: Do Young Kim, Jeong-Seok Na, Chiukin Steven Lai, Raashina Humayun, Michal Danek
  • Publication number: 20180294187
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Application
    Filed: April 9, 2018
    Publication date: October 11, 2018
    Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput
  • Publication number: 20180286746
    Abstract: Provided are methods of forming diffusion barriers and adhesion layers for interconnects such as cobalt (Co) interconnects or ruthenium (Ru) interconnects. The methods involve selective deposition of tungsten carbon nitride (WCN) films on the oxide surfaces of a feature including a Co surface. The selective growth of WCN on oxide allows the contact resistance at an interface such as a Co—Co interface or a Co—Ru interface to be significantly reduced while maintaining good film coverage, adhesion, and/or barrier properties on the sidewall oxide surfaces.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 4, 2018
    Inventors: Jeong-Seok Na, Megha Rathod, Chiukin Steven Lai, Raashina Humayun