Abstract: A chemical mechanical polishing (CMP) chamber is disclosed. The CMP chamber includes a chamber body, a door mounted on the chamber body and a chamber substructure being one selected from a group consisting of a moisture separator separating a moisture generated in the CMP chamber, a supplementary exhaust port, a transparent window mounted on the door, a sampling port mounted on the door, a sealing material including a metal frame, an o-ring for sealing the door and a combination thereof.

Abstract: A polisher includes a wafer carrier, a polishing head, a movement mechanism, and a rotation mechanism. The wafer carrier has a supporting surface. The supporting surface is configured to carry a wafer thereon. The polishing head is present above the wafer carrier. The polishing head has a polishing surface. The polishing surface of the polishing head is smaller than the supporting surface of the wafer carrier. The movement mechanism is configured to move the polishing head relative to the wafer carrier. The rotation mechanism is configured to rotate the polishing head relative to the wafer carrier.

Abstract: An apparatus for a semiconductor process includes an exhaust pipe coupled to a reaction chamber and a pump; a pressure control valve that is coupled to the exhaust pipe and configured to control a pressure value in the reaction chamber; a first pipe that is coupled to the exhaust pipe and etching gas source such that the first pipe is configured to provide an etching gas into the exhaust pipe; a second pipe that is coupled to the exhaust pipe and a radical generator such that the second pipe is configured to provide a radical into the exhaust pipe; and a third pipe that is coupled to the exhaust pipe and a diluted gas source such that the third pipe is configured to provide diluted gas into the exhaust pipe.

Abstract: A method of forming a semiconductor structure includes the following operations: (i) forming a feature comprising germanium over a substrate; (ii) removing a portion of the feature such that an interior portion of the feature is exposed; (iii) exposing a surface of the exposed interior portion to a surrounding containing oxygen; and (iv) treating the germanium oxide on the surface of the exposed interior portion with a liquid containing water.

Abstract: A control wafer making device, a method of measuring an epitaxy thickness in a control wafer, and a method for monitoring a control wafer are provided. In various embodiments, the control wafer making device includes a wafer substrate removing element and an epitaxy forming element. In various embodiments, a control wafer includes a substrate, a recess, a blocking layer, and an epitaxy. The substrate has a surface, and the recess is in the surface of the substrate. The blocking layer is over the surface of the substrate other than the recess. The epitaxy is in the recess. In various embodiments, the thickness of the epitaxy of the control wafer is measured by a polarized light.

Abstract: A control wafer making device, a method of measuring an epitaxy thickness in a control wafer, and a method for monitoring a control wafer are provided. In various embodiments, the control wafer making device includes a wafer substrate removing element and an epitaxy forming element. In various embodiments, a control wafer includes a substrate, a recess, a blocking layer, and an epitaxy. The substrate has a surface, and the recess is in the surface of the substrate. The blocking layer is over the surface of the substrate other than the recess. The epitaxy is in the recess. In various embodiments, the thickness of the epitaxy of the control wafer is measured by a polarized light.

Abstract: Among other things, one or more techniques and/or systems are provided for cleaning a polishing module of a semiconductor polishing apparatus. Purge air flow can be supplied into the polishing module (e.g., directed towards a polishing unit, a shield, and/or other polishing components) to create turbulence air flow within the polishing module. An auxiliary exhaust can be invoked to exhaust one or more particulates removed from the polishing module by the turbulence air flow. A purge air flow cycle can be performed by cycling the purge air flow and the auxiliary exhaust between on and off states. One or more purge air flow cycles can be performed during a main air flow cycle where laminar air flow is supplied into the polishing module and exhausted using a main exhaust. In this way, one or more particulates can be cleaned from the polishing module.

Abstract: A control wafer making device, a method of measuring an epitaxy thickness in a control wafer, and a method for monitoring a control wafer are provided. In various embodiments, the control wafer making device includes a wafer substrate removing element and an epitaxy forming element. In various embodiments, a control wafer includes a substrate, a recess, a blocking layer, and an epitaxy. The substrate has a surface, and the recess is in the surface of the substrate. The blocking layer is over the surface of the substrate other than the recess. The epitaxy is in the recess. In various embodiments, the thickness of the epitaxy of the control wafer is measured by a polarized light.

Abstract: An apparatus for a semiconductor process includes an exhaust pipe coupled to a reaction chamber and a pump; a pressure control valve that is coupled to the exhaust pipe and configured to control a pressure value in the reaction chamber; a first pipe that is coupled to the exhaust pipe and etching gas source such that the first pipe is configured to provide an etching gas into the exhaust pipe; a second pipe that is coupled to the exhaust pipe and a radical generator such that the second pipe is configured to provide a radical into the exhaust pipe; and a third pipe that is coupled to the exhaust pipe and a diluted gas source such that the third pipe is configured to provide diluted gas into the exhaust pipe.

Abstract: A wafer supporting structure in semiconductor manufacturing, and a device and a method for manufacturing semiconductor are provided. In accordance with some embodiments of the instant disclosure, a wafer supporting structure in semiconductor manufacturing includes a transparent ring and at least two arms. The arms are connected to the transparent ring.

Abstract: A wafer supporting structure in semiconductor manufacturing, and a device and a method for manufacturing semiconductor are provided. In accordance with some embodiments of the instant disclosure, a wafer supporting structure in semiconductor manufacturing includes a transparent ring and at least two arms. The arms are connected to the transparent ring.

Abstract: A method of forming a semiconductor structure includes the following operations: (i) forming a feature comprising germanium over a substrate; (ii) removing a portion of the feature such that an interior portion of the feature is exposed; (iii) exposing a surface of the exposed interior portion to a surrounding containing oxygen; and (iv) treating the germanium oxide on the surface of the exposed interior portion with a liquid containing water.

Abstract: A control wafer making device, a method of measuring an epitaxy thickness in a control wafer, and a method for monitoring a control wafer are provided. In various embodiments, the control wafer making device includes a wafer substrate removing element and an epitaxy forming element. In various embodiments, a control wafer includes a substrate, a recess, a blocking layer, and an epitaxy. The substrate has a surface, and the recess is in the surface of the substrate. The blocking layer is over the surface of the substrate other than the recess. The epitaxy is in the recess. In various embodiments, the thickness of the epitaxy of the control wafer is measured by a polarized light.

Abstract: A polisher includes a wafer carrier, a polishing head, a movement mechanism, and a rotation mechanism. The wafer carrier has a supporting surface. The supporting surface is configured to carry a wafer thereon. The polishing head is present above the wafer carrier. The polishing head has a polishing surface. The polishing surface of the polishing head is smaller than the supporting surface of the wafer carrier. The movement mechanism is configured to move the polishing head relative to the wafer carrier. The rotation mechanism is configured to rotate the polishing head relative to the wafer carrier.

Abstract: Methods for an oxide layer over an epitaxial layer. In an embodiment, a method includes forming an epitaxial layer of semiconductor material over a semiconductor substrate; forming an oxide layer over the epitaxial layer; applying a solution including an oxidizer to the oxide layer; and cleaning the oxide layer with a cleaning solution. In another embodiment, a densification process is applied to an oxide layer including treating with thermal energy, UV energy, or both. In an embodiment for a gate-all-around device, the cleaning process is applied to an oxide layer over an epitaxial portion of a fin. Additional methods are disclosed.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer.

Abstract: Methods for an oxide layer over an epitaxial layer. In an embodiment, a method includes forming an epitaxial layer of semiconductor material over a semiconductor substrate; forming an oxide layer over the epitaxial layer; applying a solution including an oxidizer to the oxide layer; and cleaning the oxide layer with a cleaning solution. In another embodiment, a densification process is applied to an oxide layer including treating with thermal energy, UV energy, or both. In an embodiment for a gate-all-around device, the cleaning process is applied to an oxide layer over an epitaxial portion of a fin. Additional methods are disclosed.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer.

Abstract: A chemical mechanical polishing (CMP) chamber is disclosed. The CMP chamber includes a chamber body, a door mounted on the chamber body and a chamber substructure being one selected from a group consisting of a moisture separator separating a moisture generated in the CMP chamber, a supplementary exhaust port, a transparent window mounted on the door, a sampling port mounted on the door, a sealing material including a metal frame, an o-ring for sealing the door and a combination thereof.