Abstract: Electroless NiWP layers are used for TFT Cu gate process. The NiWP deposition process comprises the following steps. (a) Cleaning of the base surface using for example UV light, ozone solution and/or alkaline mixture solution, (b) micro-etching of the base surface using, e.g. diluted acid, (c) catalyzation of the base surface using, e.g. SnCl<SUB>2</SUB> and PdCl<SUB>2</SUB> solutions, (d) conditioning of the base surface using reducing agent solution, and (e) NiWP deposition. It has been discovered that NiWP layers deposited under certain conditions could provide good adhesion to the glass substrate and to the Cu layer with a good Cu barrier capability. A NiWP layer in useful for adhesion, capping and/or barrier layers for TFT Cu gate process (e.g. for flat screen display panels).

Abstract: An interconnection structure and a fabrication method thereof. A first organic low-k material layer, a stress redistribution layer, a second organic low-k dielectric layer are formed in sequence over a substrate, followed by forming an opening in the first organic low-k material layer, the stress redistribution layer, and the second organic low-k dielectric layer. The opening is then filled with a conductive material to form an interconnection structure. The stress redistribution layer has a heat expansion coefficient closer to that of the substrate, while such heat expansion coefficient differs more significantly from those of the first and second organic low-k material layers.

Abstract: An interconnection structure and a fabrication method thereof. A first organic low-k material layer, a stress redistribution layer, a second organic low-k dielectric layer are formed in sequence over a substrate, followed by forming an opening in the first organic low-k material layer, the stress redistribution layer, and the second organic low-k dielectric layer. The opening is then filled with a conductive material to form an interconnection structure. The stress redistribution layer has a heat expansion coefficient closer to that of the substrate, while such heat expansion coefficient differs more significantly from those of the first and second organic low-k material layers.

Abstract: An interconnection structure and a fabrication method thereof. A first organic low-k material layer, a stress redistribution layer, a second organic low-k dielectric layer are formed in sequence over a substrate, followed by forming an opening in the first organic low-k material layer, the stress redistribution layer, and the second organic low-k dielectric layer. The opening is then filled with a conductive material to form an interconnection structure. The stress redistribution layer has a heat expansion coefficient closer to that of the substrate, while such heat expansion coefficient differs more significantly from those of the first and second organic low-k material layers.

Abstract: An interconnection structure and a fabrication method thereof. A first organic low-k material layer, a stress redistribution layer, a second organic low-k dielectric layer are formed in sequence over a substrate, followed by forming an opening in the first organic low-k material layer, the stress redistribution layer, and the second organic low-k dielectric layer. The opening is then filled with a conductive material to form an interconnection structure. The stress redistribution layer has a heat expansion coefficient closer to that of the substrate, while such heat expansion coefficient differs more significantly from those of the first and second organic low-k material layers.

Abstract: Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.

Abstract: A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding pads. The process can be applied in the fabrication of integrated circuits that employ copper metallization and low k dielectric materials. After patterning the final metal (aluminum) layer to form the fusible links and the bonding pads, a dielectric etch stop layer is formed over the final metal layer before a passivation layer is deposited. The passivation layer is removed in areas over the fusible links and the bonding pads. The dielectric etch stop layer is removed either from above the bonding pads only, or from above both the bonding pads and the fusible links.

Abstract: A interconnect structure and the method for fabricating the same is disclosed in this present invention. By employing a metallic compound layer, the adhesion of the cap layer to the metal layer according to this invention can be improved, and metal migration due to thermal stress in the prior art will not occur in the interconnect structure according to this invention. Furthermore, the interconnect structure and the method for manufacturing the same can efficiently keep the interconnect structure from occurring metal migration, thus no voids from thermal stress will be formed in the interconnect structure. Hence, this invention can prevent the interconnect structure from raising the resistance of the interconnect structure by the voids, and efficiently improve the reliability of the interconnect in a semiconductor structure.

Abstract: A interconnect structure and the method for fabricating the same is disclosed in this present invention. By employing a metallic compound layer, the adhesion of the cap layer to the metal layer according to this invention can be improved, and metal migration due to thermal stress in the prior art will not occur in the interconnect structure according to this invention. Furthermore, the interconnect structure and the method for manufacturing the same can efficiently keep the interconnect structure from occurring metal migration, thus no voids from thermal stress will be formed in the interconnect structure. Hence, this invention can prevent the interconnect structure from raising the resistance of the interconnect structure by the voids, and efficiently improve the reliability of the interconnect in a semiconductor structure.

Abstract: A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding pads. The process can be applied in the fabrication of integrated circuits that employ copper metallization and low k dielectric materials. After patterning the final metal (aluminum) layer to form the fusible links and the bonding pads, a dielectric etch stop layer is formed over the final metal layer before a passivation layer is deposited. The passivation layer is removed in areas over the fusible links and the bonding pads. The dielectric etch stop layer is removed either from above the bonding pads only, or from above both the bonding pads and the fusible links.

Abstract: Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.

Abstract: A method of forming metal fuses and bonding pads. A conductive layer is formed in a substrate. A dielectric layer is formed over the substrate. The dielectric layer has an opening that exposes a portion of the conductive layer. A metallic layer is formed over the dielectric layer. The metallic layer is patterned to form a metal fuse and a bonding pad. The bonding pad is electrically connected to the conductive layer via the opening. Both the metal fuse and the bonding pad have undercut sidewalls. Spacers are formed on the undercut sidewalls of the metal fuse and the bonding pad. Finally, a passivation layer that exposes the metal fuse and the bonding pad is formed over the substrate.

Abstract: The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.

Abstract: A method for forming a three dimensional semiconductor structure which has vertical capacitor(s) but not horizontal capacitor(s). The method essentially at least includes these steps of forming bottom plates within dielectric layers, forming another dielectric layer over bottom plates, removing all dielectric layers over bottom plates, forming optional liner(s) and capacitor dielectric layers on bottom plates, and forming top plates over capacitor dielectric layers. Note that shape of bottom plates is alike to the bottom connection and verticle fingers, also note that each gap within bottom plates is filled by both capacitor dielectric layer and top plate.

Abstract: A damascene process for forming a via that leads to a conductive layer on a substrate. A low dielectric constant material layer is formed over the substrate. A low temperature hard mask layer is formed over the low dielectric constant material layer. The low temperature hard mask layer is patterned to form an opening above the conductive layer. Using the low temperature hard mask layer as a mask, the exposed low dielectric constant material layer is etched to form a via hole. An adhesion promoter liner is formed on the interior walls of the via hole. Metallic material is deposited into the via hole to form a via.

Abstract: The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.

Abstract: The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.

Abstract: A method of forming metal fuses. A conductive layer is formed in a substrate. A dielectric layer is formed over the substrate. The dielectric layer has an opening that exposes a portion of the conductive layer. A metallic layer is formed over the dielectric layer. The metallic layer is patterned to form a metal fuse and a bonding pad. The bonding pad is electrically connected to the conductive layer via the opening. Both the metal fuse and the bonding pad have undercut sidewalls. Spacers are formed on the undercut sidewalls of the metal fuse and the bonding pad. Finally, a passivation layer that exposes the metal fuse and the bonding pad is formed over the substrate.

Abstract: A method that enhances performance of copper damascene by embedding TiN layer is proposed. The spirit of the invention is that a CVD TiN layer is inserted between the copper seed layer and the dielectric layer to improve the quality of copper layer. Herein, the TiN layer can either be located between the copper seed layer and the barrier layer or be located between the barrier layer and the dielectric layer. Because the barrier layer and the copper seed layer are formed by physical vapor deposition in current mass product, a higher side wall converge of the CVD TiN layer can be obtained owing to the higher conformity nature of CVD technology. Therefore, a better sidewall CVD TiN converge serves as an extra protection layer for copper self diffusion. Furthermore, it also acts as a copper seed layer to remedy side wall void problems due to copper seed layer discontinuity. Thus, not only the quality of copper layer is improved but also the performance of copper damascene process is enhanced.

Abstract: A copper-palladium alloy damascene technology applied to the ultra large scale integration (ULSI) circuits fabrication is disclosed. First, a TaN barrier is deposited over an oxide layer or in terms of the inter metal dielectric (IMD) layer. Then a copper-palladium seed is deposited over the TaN barrier. Furthermore, a copper-palladium gap-fill electroplating layer is electroplated over the dielectric oxide layer. Second, a copper-palladium annealing process is carried out. Then the copper-palladium electroplating surface is planarized by means of a chemical mechanical polishing (CMP) process. Third, the CoWP cap is self-aligned to the planarized copper-palladium alloy surface. Finally, a second IMD layer is deposited over the first IMD layer. Furthermore, a contact hole in the second dielectric layer over said CoWP cap layer is formed, and then the CoWP cap of the first IMD layer is connected with the copper-palladium alloy bottom surface of the second IMD layer directly.