Patents by Inventor Chiung-Ting Ou
Chiung-Ting Ou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11963347Abstract: A memory device includes a transistor, an anti-fuse element, a source/drain contact, a first gate via, and a second gate via. The transistor is over a substrate. The anti-fuse element is over the substrate and is connected to the transistor in series. The source/drain contact is connected to a source/drain region of the transistor. The first gate via is connected to a first gate structure of the transistor. The first gate structure of the transistor extends along a first direction in a top view. The second gate via is connected to a second gate structure of the anti-fuse element. The second gate via is between the first gate via and the source/drain contact along the first direction in the top view.Type: GrantFiled: April 21, 2023Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chiung-Ting Ou, Ming-Yih Wang, Jian-Hong Lin
-
Publication number: 20230284442Abstract: A memory device includes a transistor, an anti-fuse element, a source/drain contact, a first gate via, and a second gate via. The transistor is over a substrate. The anti-fuse element is over the substrate and is connected to the transistor in series. The source/drain contact is connected to a source/drain region of the transistor. The first gate via is connected to a first gate structure of the transistor. The first gate structure of the transistor extends along a first direction in a top view. The second gate via is connected to a second gate structure of the anti-fuse element. The second gate via is between the first gate via and the source/drain contact along the first direction in the top view.Type: ApplicationFiled: April 21, 2023Publication date: September 7, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chiung-Ting OU, Ming-Yih WANG, Jian-Hong LIN
-
Patent number: 11665890Abstract: A memory device includes a transistor, an anti-fuse element, a first gate via, a second gate via, and a bit line. The transistor includes a fin structure and a first gate structure across the fin structure. The anti-fuse element includes the fin structure and a second gate structure across the fin structure. The first gate via is connected to the first gate structure of the transistor and is spaced apart from the fin structure in a top view. The second gate via is connected to the second gate structure of the anti-fuse element and is directly above the fin structure. The bit line is connected to the fin structure and the transistor.Type: GrantFiled: August 4, 2021Date of Patent: May 30, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chiung-Ting Ou, Ming-Yih Wang, Jian-Hong Lin
-
Publication number: 20210366918Abstract: A memory device includes a transistor, an anti-fuse element, a first gate via, a second gate via, and a bit line. The transistor includes a fin structure and a first gate structure across the fin structure. The anti-fuse element includes the fin structure and a second gate structure across the fin structure. The first gate via is connected to the first gate structure of the transistor and is spaced apart from the fin structure in a top view. The second gate via is connected to the second gate structure of the anti-fuse element and is directly above the fin structure. The bit line is connected to the fin structure and the transistor.Type: ApplicationFiled: August 4, 2021Publication date: November 25, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chiung-Ting OU, Ming-Yih WANG, Jian-Hong LIN
-
Patent number: 11094702Abstract: A memory device includes a transistor, an anti-fuse element, a gate via, and a bit line. The transistor includes two source/drain regions. The anti-fuse element is connected to one of the source/drain regions of the transistor. The anti-fuse element includes a channel and a gate structure above the channel. The gate via is above the gate structure of the anti-fuse element. A lateral distance between a center of the gate via and a sidewall of the channel is less than a width of the gate via. The bit line is connected to another of the source/drain regions of the transistor.Type: GrantFiled: February 10, 2020Date of Patent: August 17, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chiung-Ting Ou, Ming-Yih Wang, Jian-Hong Lin
-
Publication number: 20210249421Abstract: A memory device includes a transistor, an anti-fuse element, a gate via, and a bit line. The transistor includes two source/drain regions. The anti-fuse element is connected to one of the source/drain regions of the transistor. The anti-fuse element includes a channel and a gate structure above the channel. The gate via is above the gate structure of the anti-fuse element. A lateral distance between a center of the gate via and a sidewall of the channel is less than a width of the gate via. The bit line is connected to another of the source/drain regions of the transistor.Type: ApplicationFiled: February 10, 2020Publication date: August 12, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chiung-Ting OU, Ming-Yih WANG, Jian-Hong LIN
-
Patent number: 8659072Abstract: A device includes a first semiconductor fin, and a second semiconductor fin parallel to the first semiconductor fin. A straight gate electrode is formed over the first and the second semiconductor fins, and forms a first fin field-effect transistor (FinFET) and a second FinFET with the first and the second semiconductor fins, respectively, wherein the first and the second FinFETs are of a same conductivity type. A first electrical connection is formed on a side of the straight gate electrode and coupling a first source/drain of the first FinFET to a first source/drain of the second FinFET, wherein a second source/drain of the first FinFET is not connected to a second source/drain of the second FinFET.Type: GrantFiled: September 24, 2010Date of Patent: February 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiung-Ting Ou, Chih-Chiang Chang
-
Publication number: 20120074495Abstract: A device includes a first semiconductor fin, and a second semiconductor fin parallel to the first semiconductor fin. A straight gate electrode is formed over the first and the second semiconductor fins, and forms a first fin field-effect transistor (FinFET) and a second FinFET with the first and the second semiconductor fins, respectively, wherein the first and the second FinFETs are of a same conductivity type. A first electrical connection is formed on a side of the straight gate electrode and coupling a first source/drain of the first FinFET to a first source/drain of the second FinFET, wherein a second source/drain of the first FinFET is not connected to a second source/drain of the second FinFET.Type: ApplicationFiled: September 24, 2010Publication date: March 29, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiung-Ting Ou, Chih-Chiang Chang
-
Patent number: 8111792Abstract: Circuits and methods for performing adaptive frequency compensation in a serial receiver coupled to a differential signal channel link are disclosed. In an exemplary embodiment, a receiver for signals over a serial channel link is provided including a linear equalization function. A data recovery circuit is coupled to the output of the receiver and receives frequency compensated analog signals. A digital feedback control circuit observes the digital output. A data accumulator circuit receives the output of a comparator and a signal indicating the data pattern observed in the digital data output. A digital filter receives the accumulator data and outputs control signals for modifying the linear equalization in a feedback loop. The receiver and linear equalization function are automatically and adaptively modified to provide frequency compensation. Methods for adaptively modifying the frequency response of a receiver and linear equalizer using digital feedback are disclosed.Type: GrantFiled: December 8, 2009Date of Patent: February 7, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chiung-Ting Ou
-
Patent number: 8026743Abstract: An envelope detecting circuit is provided. The envelope detecting circuit comprises a source degeneration circuit that amplifies an input differential signal, a differential gain stage that supplies a voltage proportional to the amplified signal, a potential hold circuit that holds the voltage supplied from the gain stage, a comparator circuit that compares the voltage held by the potential holding circuit with a reference potential to output a detect signal, and envelope level adjustment and selection unit that responds to the detect signal and outputs a control signal to the source degeneration circuit.Type: GrantFiled: December 14, 2010Date of Patent: September 27, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chiung-Ting Ou
-
Publication number: 20110084762Abstract: An envelope detecting circuit is provided. The envelope detecting circuit comprises a source degeneration circuit that amplifies an input differential signal, a differential gain stage that supplies a voltage proportional to the amplified signal, a potential hold circuit that holds the voltage supplied from the gain stage, a comparator circuit that compares the voltage held by the potential holding circuit with a reference potential to output a detect signal, and envelope level adjustment and selection unit that responds to the detect signal and outputs a control signal to the source degeneration circuit.Type: ApplicationFiled: December 14, 2010Publication date: April 14, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chiung-Ting Ou
-
Patent number: 7863940Abstract: An envelope detecting circuit is provided. The envelope detecting circuit comprises a source degeneration circuit that amplifies an input differential signal, a differential gain stage that supplies a voltage proportional to the amplified signal, a potential hold circuit that holds the voltage supplied from the gain stage, a comparator circuit that compares the voltage held by the potential holding circuit with a reference potential to output a detect signal, and envelope level adjustment and selection unit that responds to the detect signal and outputs a control signal to the source degeneration circuit.Type: GrantFiled: August 15, 2008Date of Patent: January 4, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chiung-Ting Ou
-
Publication number: 20100246657Abstract: Circuits and methods for performing adaptive frequency compensation in a serial receiver coupled to a differential signal channel link are disclosed. In an exemplary embodiment, a receiver for signals over a serial channel link is provided including a linear equalization function. A data recovery circuit is coupled to the output of the receiver and receives frequency compensated analog signals. A digital feedback control circuit observes the digital output. A data accumulator circuit receives the output of a comparator and a signal indicating the data pattern observed in the digital data output. A digital filter receives the accumulator data and outputs control signals for modifying the linear equalization in a feedback loop. The receiver and linear equalization function are automatically and adaptively modified to provide frequency compensation. Methods for adaptively modifying the frequency response of a receiver and linear equalizer using digital feedback are disclosed.Type: ApplicationFiled: December 8, 2009Publication date: September 30, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chiung-Ting Ou
-
Publication number: 20100039141Abstract: An envelope detecting circuit is provided. The envelope detecting circuit comprises a source degeneration circuit that amplifies an input differential signal, a differential gain stage that supplies a voltage proportional to the amplified signal, a potential hold circuit that holds the voltage supplied from the gain stage, a comparator circuit that compares the voltage held by the potential holding circuit with a reference potential to output a detect signal, and envelope level adjustment and selection unit that responds to the detect signal and outputs a control signal to the source degeneration circuit.Type: ApplicationFiled: August 15, 2008Publication date: February 18, 2010Inventor: Chiung-Ting Ou
-
Patent number: 7349681Abstract: A self-biased high-speed receiver is described. The receiver is powered by one power supply with the core operation voltage and one power supply with the IO operation voltage. The receiver is self-biased to provide a stable bias voltage. A reference voltage and an IO signal are applied on the receiver so that the difference is amplified. Thick oxide transistors are used to increase the operation voltage of the transistors. Native thick oxide transistors are used so that the receiver can work with low command mode input.Type: GrantFiled: July 13, 2004Date of Patent: March 25, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chiung-Ting Ou
-
Publication number: 20060014514Abstract: A self-biased high-speed receiver is described. The receiver is powered by one power supply with the core operation voltage and one power supply with the IO operation voltage. The receiver is self-biased to provide a stable bias voltage. A reference voltage and an IO signal are applied on the receiver so that the difference is amplified. Thick oxide transistors are used to increase the operation voltage of the transistors. Native thick oxide transistors are used so that the receiver can work with low command mode input.Type: ApplicationFiled: July 13, 2004Publication date: January 19, 2006Inventor: Chiung-Ting Ou
-
Publication number: 20030122647Abstract: An inductor formed on a silicon substrate. The inductor includes a silicon substrate; a plurality of first metal lines formed parallel with each other on the silicon substrate; a plurality of via plugs formed at the two ends of each first metal line; and a plurality of third metal lines formed parallel with each other on the via plugs. The two ends of each third metal line are connected to the two ends of each first metal line through the via plugs, such that a spiral circuit is formed.Type: ApplicationFiled: September 5, 2002Publication date: July 3, 2003Inventor: Chiung-Ting Ou
-
Publication number: 20030122648Abstract: An inductor with an enclosed magnetic flux pattern. The inductor includes a semiconductor substrate; a first mask pattern formed on the semiconductor substrate; an inductor coil formed on the first mask pattern; and a second mask pattern formed on the inductor coil and connected to the first mask pattern through a plurality of plugs, such that an enclosed magnetic flux pattern is formed around the inductor coil.Type: ApplicationFiled: September 16, 2002Publication date: July 3, 2003Inventors: Chiung-Ting Ou, Yu-Chen Lin
-
Publication number: 20020093414Abstract: A semiconductor device including a substrate, a polysilicon shield layer having a plurality of dielectric sections disposed over the substrate and the plurality of dielectric sections being of a geometric shape, and an inductor including a first metallic layer disposed over the polysilicon layer wherein the first metallic layer overlaps a number of the plurality of dielectric sections and each of the plurality of dielectric sections is of a proximity from one another to substantially reduce or prevent mirror current from being formed in the shield layer.Type: ApplicationFiled: January 17, 2001Publication date: July 18, 2002Applicant: Winbond Electronics CorporationInventors: Shyh-chyi Wong, Chiung-Ting Ou