Patents by Inventor Chiung-Yuan LIN

Chiung-Yuan LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12154828
    Abstract: A semiconductor device includes a substrate, a 2-D material layer, source/drain contacts, and a gate electrode. The 2-D material layer is over the substrate, the 2-D material layer includes source/drain regions and a channel region between the source/drain regions, in which the 2-D material layer is made of a transition metal dichalcogenide (TMD). The source/drain contacts are in contact with source/drain regions of the 2-D material layer, in which a binding energy of transition metal atoms at the channel region of the 2-D material layer is different from a binding energy of the transition metal atoms at the source/drain regions of the 2-D material layer. The gate electrode is over the substrate.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: November 26, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chiung-Yuan Lin, Tsung-Fu Yang, Weicheng Chu, Ching Liang Chang, Chen Han Chou, Chia-Ho Yang, Tsung-Kai Lin, Tsung-Han Lin, Chih-Hung Chung, Chenming Hu
  • Publication number: 20230023186
    Abstract: A semiconductor device includes a substrate, a 2-D material layer, source/drain contacts, and a gate electrode. The 2-D material layer is over the substrate, the 2-D material layer includes source/drain regions and a channel region between the source/drain regions, in which the 2-D material layer is made of a transition metal dichalcogenide (TMD). The source/drain contacts are in contact with source/drain regions of the 2-D material layer, in which a binding energy of transition metal atoms at the channel region of the 2-D material layer is different from a binding energy of the transition metal atoms at the source/drain regions of the 2-D material layer. The gate electrode is over the substrate.
    Type: Application
    Filed: January 13, 2022
    Publication date: January 26, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., National Yang Ming Chiao Tung University
    Inventors: Chiung-Yuan LIN, Tsung-Fu YANG, Weicheng CHU, Ching Liang CHANG, Chen Han CHOU, Chia-Ho YANG, Tsung-Kai LIN, Tsung-Han LIN, Chih-Hung CHUNG, Chenming HU