Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.

Abstract: The present disclosure provides a semiconductor device and a method for forming a semiconductor device. The semiconductor device includes a substrate, and a first gate dielectric stack over the substrate, wherein the first gate dielectric stack includes a first ferroelectric layer, and a first dielectric layer coupled to the first ferroelectric layer, wherein the first ferroelectric layer includes a first portion made of a ferroelectric material in orthorhombic phase, a second portion made of the ferroelectric material in monoclinic phase, and a third portion made of the ferroelectric material in tetragonal phase, wherein a total volume of the second portion is greater than a total volume of the first portion, and the total volume of the first portion is greater than a total volume of the third portion.

Abstract: A signal line conversion structure of the antenna array is disposed between the antenna array and the circuit substrate, which includes a first dielectric substrate is disposed on the circuit substrate, a second dielectric substrate is vertically disposed on the first dielectric substrate and divided into a first region and a second region, and the second dielectric substrate is provided with the antenna array. At least one signal line is disposed on the first region and extends to the second dielectric substrate for connecting the circuit substrate and the antenna array. A metal connecting plate has at least three metal through holes pierced in the first dielectric substrate and connected to the second ground layer. The metal connecting plate is connected to the first ground layer of the first dielectric substrate and the second ground layer of the second dielectric substrate through the metal through holes.

Abstract: A signal line conversion structure of the antenna array is disposed between the antenna array and the circuit substrate, which includes a first dielectric substrate is disposed on the circuit substrate, a second dielectric substrate is vertically disposed on the first dielectric substrate and divided into a first region and a second region, and the second dielectric substrate is provided with the antenna array. At least one signal line is disposed on the first region and extends to the second dielectric substrate for connecting the circuit substrate and the antenna array. A metal connecting plate has at least three metal through holes pierced in the first dielectric substrate and connected to the second ground layer. The metal connecting plate is connected to the first ground layer of the first dielectric substrate and the second ground layer of the second dielectric substrate through the metal through holes.

Abstract: A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.

Abstract: A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.

Abstract: The parallel-coupled-resonator coupled line filter with open-and-short end, comprises an input port for receiving an input signal; a bent first resonator and a bent third resonator where their both ends are open circuited; a second resonator whose both ends are shorted to ground; and an output port for outputting signal. Wherein, designing cross coupling between the third resonator and the first resonator to obtain a steep frequency response and reduce the interference of the image signal.

Abstract: The parallel-coupled-resonator coupled line filter with open-and-short end, comprises an input port for receiving an input signal; a bent first resonator and a bent third resonator where their both ends are open circuited; a second resonator whose both ends are shorted to ground; and an output port for outputting signal. Wherein, designing cross coupling between the third resonator and the first resonator to obtain a steep frequency response and reduce the interference of the image signal.

Abstract: A balun-transformer, which is composed of a balun transition and an impedance matching circuit. Chemical etching is employed in the manufacturing process that is compatible with the common microwave circuit manufacturing process. Using the odd mode analysis and commercial microwave software to design the balun-transformer. It is more accurate and more efficient than the conventional method to make balun-transformer that it can only be designed by experience and experiments. These balun-transformers can be used in UHF and VHF band.

Abstract: A balun-transformer, which is composed of a balun transition and an impedance matching circuit. Chemical etching is employed in the manufacturing process that is compatible with the common microwave circuit manufacturing process. Using the odd mode analysis and commercial microwave software to design the balun-transformer, It is more accurate and more efficient than the conventional method to make balun-transformer that it can only be designed by experience and experiments. These balun-transformers can be used in UHF and VHF band.