Abstract: An example apparatus is for use in calibration of a test system having multiple channels and a socket for receiving a device under test. The example apparatus includes a device interface that is connectable to the socket; and multiple circuit paths, where each circuit path is connectable, through the device interface, to a corresponding channel of the test system and being connected to a common node. The example apparatus is configured so that, during calibration, signals either (i) each pass from the test system, through one of the multiple circuit paths, and back to the test system through others of the multiple circuit paths, or (ii) each pass from the test system, through the others of the multiple circuit paths, and back to the test system through the one of the multiple circuit paths.

Abstract: An example apparatus is for use in calibration of a test system having multiple channels and a socket for receiving a device under test. The example apparatus includes a device interface that is connectable to the socket; and multiple circuit paths, where each circuit path is connectable, through the device interface, to a corresponding channel of the test system and being connected to a common node. The example apparatus is configured so that, during calibration, signals either (i) each pass from the test system, through one of the multiple circuit paths, and back to the test system through others of the multiple circuit paths, or (ii) each pass from the test system, through the others of the multiple circuit paths, and back to the test system through the one of the multiple circuit paths.

Abstract: Automatic test equipment is disclosed for testing a semiconductor device and including a computer workstation and pin electronics circuitry coupled between the semiconductor device and the computer. The pin electronics circuitry includes a plurality of channels, each channel having timing circuitry operative in response to desired programmed timing information, driver/comparator circuitry coupled to the timing circuitry for driving test waveforms at a period T, and sampling data from the waveforms at a beat period T +/−&Dgr;t, and a timing measurement unit. The timing measurement unit is coupled to the driver/comparator circuitry for measuring the relative timings of the sampled data. The plurality of channels cooperate to produce substantially real-time timing measurement data in parallel.