Patents by Inventor Chizu Matsumoto

Chizu Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9147913
    Abstract: Manufacturing management information relating to a module battery and single battery mounted therein which are obtained in a battery manufacturing process (1) is collected by a manufacturing quality information collection processing unit (4) and stored in a database (6). In a battery diagnosis system (3), when the module battery (2) under a usage environment is charged, an operation result processing unit (5) collects operation result information relating to the module (2) and stores the operation result information in a database (7). An operation result monitoring processing unit (8) determines whether the operation result information is abnormal, and supplies the result of the determination to a manufacturing/usage environment factor classification processing unit (9).
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: September 29, 2015
    Assignee: HITACHI, LTD.
    Inventors: Toshiharu Miwa, Seiji Ishikawa, Chizu Matsumoto
  • Patent number: 8612811
    Abstract: In a managing system for a semiconductor manufacturing apparatus, a predicting unit 121 predicts a characteristic defective ratio and a foreign-substance defective ratio of each process obtains an actual defective ratio of each fail bit mode and a critical area of each process and each fail bit mode, calculates the number of foreign substances of each process by using the actual defective ratio of each fail bit mode and the critical area of each process and each fail bit mode, the fail bit mode being except for an arbitrary fail bit mode, calculates a foreign-substance defective ratio of each process and a foreign-substance defective ratio of each fail bit mode by using the number of foreign substances, and calculates a characteristic defective ratio of the arbitrary fail bit mode based on the foreign-substance defective ratio and actual defective ratio of each fail bit mode.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: December 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Chizu Matsumoto, Yuichi Hamamura, Yoshiyuki Tsunoda, Kazuyuki Tsunokuni
  • Patent number: 8400853
    Abstract: A repair circuit achieving “group repair of mixed multiple repair methods” and a repair design method for making a product margin suitable are provided. In a chip mounting multiple RAMs, a repair circuit and a repair design method in consideration of a trade-off of chip yield and area increase along with mounting a repair circuit are provided. A repair circuit achieving “group repair of mixed multiple repair methods” which can select existence of a repair circuit, and one or more repair methods from I/O, column, and row repairs on the RAMS in the chip, respectively, when a repair circuit is mounted. The repair circuit performs repair per RAM group by sorting the RAMs mounting a repair circuit into a plurality of RAM groups. Also, a repair method which makes a number of acquired good chips in a wafer and an estimation method of the RAM grouping method are provided.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: March 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Chizu Matsumoto, Kaname Yamasaki, Michinobu Nakao, Yoshikazu Saitou
  • Publication number: 20120259569
    Abstract: Manufacturing management information relating to a module battery and single battery mounted therein which are obtained in a battery manufacturing process (1) is collected by a manufacturing quality information collection processing unit (4) and stored in a database (6). In a battery diagnosis system (3), when the module battery (2) under a usage environment is charged, an operation result processing unit (5) collects operation result information relating to the module (2) and stores the operation result information in a database (7). An operation result monitoring processing unit (8) determines whether the operation result information is abnormal, and supplies the result of the determination to a manufacturing/usage environment factor classification processing unit (9).
    Type: Application
    Filed: November 8, 2010
    Publication date: October 11, 2012
    Inventors: Toshiharu Miwa, Seiji Ishikawa, Chizu Matsumoto
  • Publication number: 20110172806
    Abstract: In a managing system for a semiconductor manufacturing apparatus, a predicting unit 121 predicts a characteristic defective ratio and a foreign-substance defective ratio of each process obtains an actual defective ratio of each fail bit mode and a critical area of each process and each fail bit mode, calculates the number of foreign substances of each process by using the actual defective ratio of each fail bit mode and the critical area of each process and each fail bit mode, the fail bit mode being except for an arbitrary fail bit mode, calculates a foreign-substance defective ratio of each process and a foreign-substance defective ratio of each fail bit mode by using the number of foreign substances, and calculates a characteristic defective ratio of the arbitrary fail bit mode based on the foreign-substance defective ratio and actual defective ratio of each fail bit mode.
    Type: Application
    Filed: September 4, 2009
    Publication date: July 14, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Chizu Matsumoto, Yuichi Hamamura, Yoshiyuki Tsunoda, Kazuyuki Tsunokuni
  • Publication number: 20100290299
    Abstract: A repair circuit achieving “group repair of mixed multiple repair methods” and a repair design method for making a product margin suitable are provided. In a chip mounting multiple RAMs, a repair circuit and a repair design method in consideration of a trade-off of chip yield and area increase along with mounting a repair circuit are provided. A repair circuit achieving “group repair of mixed multiple repair methods” which can select existence of a repair circuit, and one or more repair methods from I/O, column, and row repairs on the RAMS in the chip, respectively, when a repair circuit is mounted. The repair circuit performs repair per RAM group by sorting the RAMs mounting a repair circuit into a plurality of RAM groups. Also, a repair method which makes a number of acquired good chips in a wafer and an estimation method of the RAM grouping method are provided.
    Type: Application
    Filed: May 12, 2010
    Publication date: November 18, 2010
    Inventors: Chizu MATSUMOTO, Kaname Yamasaki, Michinobu Nakao, Yoshikazu Saitou