Abstract: In a general aspect, a laterally diffused metal-oxide-semiconductor (LDMOS) transistor can include: a substrate of a first conductivity type; a buried well region of a second conductivity type disposed in the substrate; a body region of the first conductivity type disposed on the buried well region, a drift region of the second conductivity type disposed in the body region, a drain implant of the second conductivity type disposed in the drift region; a source implant of the second conductivity type disposed in the body region; and a gate structure disposed on the drift region. The gate structure can include: a field plate including a RESURF dielectric layer; a gate dielectric layer; and a gate electrode disposed on the field plate and the gate dielectric layer. The LDMOS transistor can also include a drain contact extending through the field plate and defining an Ohmic contact with the drain implant.

Abstract: In a general aspect, a laterally diffused metal-oxide-semiconductor (LDMOS) transistor can include: a substrate of a first conductivity type; a buried well region of a second conductivity type disposed in the substrate; a body region of the first conductivity type disposed on the buried well region, a drift region of the second conductivity type disposed in the body region, a drain implant of the second conductivity type disposed in the drift region; a source implant of the second conductivity type disposed in the body region; and a gate structure disposed on the drift region. The gate structure can include: a field plate including a RESURF dielectric layer; a gate dielectric layer; and a gate electrode disposed on the field plate and the gate dielectric layer. The LDMOS transistor can also include a drain contact extending through the field plate and defining an Ohmic contact with the drain implant.

Abstract: A lateral trench MOSFET includes a trench containing a device segment and a gate bus segment. The gate bus segment of the trench is contacted by a conductive plug formed in a dielectric layer overlying the substrate, thereby avoiding the need for the conventional surface polysilicon bridge layer. The conductive plug is formed in a substantially vertical hole in the dielectric layer. The gate bus segment may be wider than the device segment of the trench. A method includes forming a shallow trench isolation (STI) while the conductive material in the trench is etched.

Abstract: A lateral trench MOSFET includes a trench containing a device segment and a gate bus segment. The gate bus segment of the trench is contacted by a conductive plug formed in a dielectric layer overlying the substrate, thereby avoiding the need for the conventional surface polysilicon bridge layer. The conductive plug is formed in a substantially vertical hole in the dielectric layer. The gate bus segment may be wider than the device segment of the trench. A method includes forming a shallow trench isolation (STI) while the conductive material in the trench is etched.

Abstract: A lateral trench MOSFET includes a trench containing a device segment and a gate bus segment. The gate bus segment of the trench is contacted by a conductive plug formed in a dielectric layer overlying the substrate, thereby avoiding the need for the conventional surface polysilicon bridge layer. The conductive plug is formed in a substantially vertical hole in the dielectric layer. The gate bus segment may be wider than the device segment of the trench. A method includes forming a shallow trench isolation (STI) while the conductive material in the trench is etched.

Abstract: A lateral trench MOSFET includes a trench containing a device segment and a gate bus segment. The gate bus segment of the trench is contacted by a conductive plug formed in a dielectric layer overlying the substrate, thereby avoiding the need for the conventional surface polysilicon bridge layer. The conductive plug is formed in a substantially vertical hole in the dielectric layer. The gate bus segment may be wider than the device segment of the trench. A method includes forming a shallow trench isolation (STI) while the conductive material in the trench is etched.