Abstract: A signal receiving device is adapted for receiving a multi-bit signal-under-test that supports one of first and second base frequency types, and outputting a type indicator for indicating which one of the first and second base frequency types is supported by the signal-under-test. The signal receiving device includes a counter and a frequency determining circuit. The counter includes an accumulating unit for counting cycles of an operating clock so as to obtain a bit count. The frequency determining circuit is coupled to the counter for comparing the bit count to one of first and second preset values in accordance with a previous value of the type indicator so as to obtain a comparison result, and determining whether to update a value of the type indicator based on the comparison result.

Abstract: A signal receiving device is adapted for receiving a multi-bit signal-under-test that supports one of first and second base frequency types, and outputting a type indicator for indicating which one of the first and second base frequency types is supported by the signal-under-test. The signal receiving device includes a counter and a frequency determining circuit. The counter includes an accumulating unit for counting cycles of an operating clock so as to obtain a bit count. The frequency determining circuit is coupled to the counter for comparing the bit count to one of first and second preset values in accordance with a previous value of the type indicator so as to obtain a comparison result, and determining whether to update a value of the type indicator based on the comparison result.