Abstract: A method of performing an optimization within a circuit layout design is provided. The method includes determining, from multiple nets of the circuit layout design, a target net that has one or more performance characteristics that are outside a range of constraints, determining, from the multiple nets, a non-critical net that has the one or more performance characteristics that are within the range of the constraints, and adjusting, by a processor, one or more of a shape and a location of one or more of the non-critical net and the target net, such that the one or more performance characteristics of the non-critical net is changed and remains within the range of the constraints.

Abstract: Modes of a circuit are merged together to reduce the number of modes. Subsets of modes are identified such that modes belonging to each subset are mergeable. A set of modes is mergeable if every pair of modes in the set is mergeable. Constraints of modes belonging to each pair of modes are compared to determine whether two modes are mergeable. To allow two modes to be merged, a constraint is transformed such that it affects the same paths in the merged mode and the first mode but excludes paths from the second mode. Determining whether two modes are mergeable may include verifying whether a clock in one mode blocks propagation of a clock in another mode and whether a value specified in a constraint in a mode is within specified tolerance of the value of a corresponding constraint in another mode.

Abstract: Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are identified in the merged mode and eliminated by introducing timing constraints in the merged mode. Equivalence between the merged mode and the individual modes is verified by comparing timing relationships in the merged mode with timing relationships in the individual modes. The merged mode is considered equivalent to the individual modes if every timing relationship present in an individual mode is present in the merged mode and every timing relationship present in the merged mode is present in any of individual modes.

Abstract: Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are identified in the merged mode and eliminated by introducing timing constraints in the merged mode. Equivalence between the merged mode and the individual modes is verified by comparing timing relationships in the merged mode with timing relationships in the individual modes. The merged mode is considered equivalent to the individual modes if every timing relationship present in an individual mode is present in the merged mode and every timing relationship present in the merged mode is present in any of individual modes.

Abstract: Modes of a circuit are merged together to reduce the number of modes. Subsets of modes are identified such that modes belonging to each subset are mergeable. A set of modes is mergeable if every pair of modes in the set is mergeable. Constraints of modes belonging to each pair of modes are compared to determine whether two modes are mergeable. To allow two modes to be merged, a constraint is transformed such that it affects the same paths in the merged mode and the first mode but excludes paths from the second mode. Determining whether two modes are mergeable may include verifying whether a clock in one mode blocks propagation of a clock in another mode and whether a value specified in a constraint in a mode is within specified tolerance of the value of a corresponding constraint in another mode.

Abstract: Timing behaviors associated with constraints of circuits are compared to identify mismatches between circuit configurations. Aggregate sets of timing constraints associated with timing nodes are determined for timing paths between start points and end points. Precedence rules are applied to aggregate sets of timing constraints by applying precedence rules to interacting timing constraints. Aggregate sets of constraints for corresponding timing nodes are matched to determine if timing constraint mismatches exist between circuits. If aggregate timing constraints associated with start point, end point pairs are found to match, reconvergent points between the start point and end points are analyzed to see if aggregate constraints of timing nodes connected to reconvergent/divergent points match if timing exception matches are involved. Graph traversal algorithms allow efficient computation of aggregate timing constraints for timing nodes.

Abstract: Timing behaviors associated with constraints of circuits are compared to identify mismatches between circuit configurations. Aggregate sets of timing constraints associated with timing nodes are determined for timing paths between start points and end points. Precedence rules are applied to aggregate sets of timing constraints by applying precedence rules to interacting timing constraints. Aggregate sets of constraints for corresponding timing nodes are matched to determine if timing constraint mismatches exist between circuits. If aggregate timing constraints associated with start point, end point pairs are found to match, reconvergent points between the start point and end points are analyzed to see if aggregate constraints of timing nodes connected to reconvergent/divergent points match if timing exception matches are involved. Graph traversal algorithms allow efficient computation of aggregate timing constraints for timing nodes.

Abstract: Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are identified in the merged mode and eliminated by introducing timing constraints in the merged mode. Equivalence between the merged mode and the individual modes is verified by comparing timing relationships in the merged mode with timing relationships in the individual modes. The merged mode is considered equivalent to the individual modes if every timing relationship present in an individual mode is present in the merged mode and every timing relationship present in the merged mode is present in any of individual modes.

Abstract: Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are identified in the merged mode and eliminated by introducing timing constraints in the merged mode. Equivalence between the merged mode and the individual modes is verified by comparing timing relationships in the merged mode with timing relationships in the individual modes. The merged mode is considered equivalent to the individual modes if every timing relationship present in an individual mode is present in the merged mode and every timing relationship present in the merged mode is present in any of individual modes.