Patents by Inventor Cho Woo Moon

Cho Woo Moon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7356451
    Abstract: Disclosed is a method and system for handling timing constraints or assertions for timing model extraction. One disclosed approach for assertion handling is by automatically preserving the integrity of original assertions by retaining existing pins or creating new internal pins. The assertions are viewed as part of the model, and a set of new assertions are generated automatically as part of the timing model extraction process and can be stored as part of the model. Assertions can be associated with input ports, output ports, internal pins, or hierarchical pins and can even span multiple blocks. This disclosed approach allows for application of assertions associated with timing models when the model is instantiated and detachment of assertions when the model is de-instantiated, and thus removes one of main problems associated with timing models.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: April 8, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Cho Woo Moon, Harish Kriplani, Krishna Prasad Belkhale
  • Patent number: 6928630
    Abstract: Disclosed is a method and system for extracting a timing model. One disclosed approach to extract a timing model is by reducing the timing graph. Original timing behavior is preserved in the timing model including arrival times, slew times, timing violations and even latch time borrowing that is independent of clock waveforms. Also, original timing constraints can be captured in the model and be applied automatically when the model is used. Anchor points are automatically identified and retained to obtain a model that is smaller than the original netlist.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: August 9, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Cho Woo Moon, Harish Kriplani, Krishna Prasad Belkhale
  • Publication number: 20030120474
    Abstract: Disclosed is a method and system for handling timing constraints or assertions for timing model extraction. One disclosed approach for assertion handling is by automatically preserving the integrity of original assertions by retaining existing pins or creating new internal pins. The assertions are viewed as part of the model, and a set of new assertions are generated automatically as part of the timing model extraction process and can be stored as part of the model. Assertions can be associated with input ports, output ports, internal pins, or hierarchical pins and can even span multiple blocks. This disclosed approach allows for application of assertions associated with timing models when the model is instantiated and detachment of assertions when the model is de-instantiated, and thus removes one of main problems associated with timing models.
    Type: Application
    Filed: December 6, 2002
    Publication date: June 26, 2003
    Applicant: Cadence Design Systems, Inc.
    Inventors: Cho Woo Moon, Harish Kriplani, Krishna Prasad Belkhale
  • Publication number: 20030121013
    Abstract: Disclosed is a method and system for extracting a timing model. One disclosed approach to extract a timing model is by reducing the timing graph. Original timing behavior is preserved in the timing model including arrival times, slew times, timing violations and even latch time borrowing that is independent of clock waveforms. Also, original timing constraints can be captured in the model and be applied automatically when the model is used. Anchor points are automatically identified and retained to obtain a model that is smaller than the original netlist.
    Type: Application
    Filed: December 6, 2002
    Publication date: June 26, 2003
    Applicant: Cadence Design Systems, Inc.
    Inventors: Cho Woo Moon, Harish Kriplani, Krishna Prasad Belkhale