Abstract: A semiconductor device includes a memory cell region positioned on a substrate and comprising a real memory cell region and a dummy memory cell region; and a connection region extending in a first direction parallel to a surface of the substrate in the memory cell region. The dummy memory cell region includes a plurality of dummy vertical channel structures spaced apart from each other. Each of the plurality of dummy vertical channel structures includes a vertical channel pattern in contact with the substrate while penetrating a stack structure comprising a plurality of insulating layers and a plurality of gate electrodes repeatedly stacked in a third direction perpendicular to a surface of the substrate. A protection pattern is disposed to surround the vertical channel pattern of at least one of the plurality of dummy vertical channel structures.

Abstract: A semiconductor device of the disclosure includes a peripheral circuit structure including a peripheral transistor, a semiconductor layer on the peripheral circuit structure, a source structure on the semiconductor layer, a gate stack structure on the source structure, the gate stack structure including a word line, a gate upper line and a staircase structure, a memory channel structure and a dummy channel structure extending through the gate stack structure, a cut structure extending through the gate upper line, and a bit line overlapping with the memory channel structure. The cut structure includes a narrow section, and a wide section nearer to the staircase structure than the narrow section. A width of the narrow section is less than a width of the wide section.

Abstract: An integrated circuit device comprising: a substrate; a stack structure comprising interlayer insulating layers and gate electrodes; and a channel structure in the stack structure, wherein the gate electrodes comprise a first upper gate electrode at a highest position and a second upper gate electrode at a second-highest position, the interlayer insulating layers comprises a first interlayer insulating layer between the first upper gate electrode and the second upper gate electrode with a first thickness, a second interlayer insulating layer that has a second thickness, a lower surface of the first upper gate electrode is at a farther distance than or at an equal distance to a lower surface of the pad structure from the substrate, and an upper surface of the second upper gate electrode is at a closer distance than or at an equal distance to the lower surface of the pad structure from the substrate.

Abstract: Disclosed are semiconductor devices, electronic systems including the same, and methods of fabricating the same. The semiconductor device comprises a source structure that includes a support source layer, a gate stack structure on the support source layer, a memory channel structure that penetrates through the gate stack structure and the support source layer, and a separation structure that penetrates through the gate stack structure and the support source layer. The support source layer includes a first source part through which the memory channel structure penetrates, and a second source part through which the separation structure penetrates. A top surface of the first source part is at a level lower than that of a top surface of the second source part.

Abstract: A semiconductor device includes a memory cell region positioned on a substrate and comprising a real memory cell region and a dummy memory cell region; and a connection region extending in a first direction parallel to a surface of the substrate in the memory cell region. The dummy memory cell region includes a plurality of dummy vertical channel structures spaced apart from each other. Each of the plurality of dummy vertical channel structures includes a vertical channel pattern in contact with the substrate while penetrating a stack structure comprising a plurality of insulating layers and a plurality of gate electrodes repeatedly stacked in a third direction perpendicular to a surface of the substrate. A protection pattern is disposed to surround the vertical channel pattern of at least one of the plurality of dummy vertical channel structures.

Abstract: A semiconductor device of the disclosure includes a peripheral circuit structure including a peripheral transistor, a semiconductor layer on the peripheral circuit structure, a source structure on the semiconductor layer, a gate stack structure on the source structure, the gate stack structure including a word line, a gate upper line and a staircase structure, a memory channel structure and a dummy channel structure extending through the gate stack structure, a cut structure extending through the gate upper line, and a bit line overlapping with the memory channel structure. The cut structure includes a narrow section, and a wide section nearer to the staircase structure than the narrow section. A width of the narrow section is less than a width of the wide section.

Abstract: A semiconductor device may include a first cell block including a first electrode structure including first electrodes stacked on a substrate, and first channels penetrating the first electrode structure, and a second cell block including a second electrode structure including second electrodes stacked on the substrate, and second channels penetrating the second electrode structure. The first and second electrode structures may extend in a first direction. The first electrode structure may have a first width in a second direction, and the second electrode structure may have a second width greater than the first width. A side surface of the first electrode structure and the first channel adjacent thereto may be apart from each other by a first distance, and a side surface of the second electrode structure and the second channel adjacent thereto may be apart from each other by a second distance different from the first distance.